Datasheet > ATF1508BE-5AX100

ATF1508BE-5AX100

更新时间： 2022-12-16 18:35:14

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ATF1508BE-5AX100 数据手册

ATF1508BE

Figure 2-2. I/O with Programmable Pin-keeper

V_CCIO

V_CCINT

50K

2.2

2.3

Schmitt Trigger

The Input Buffer of each input and I/O pin has an optional schmitt trigger setting. The schmitt

trigger option can be used to buffer inputs with slow rise times.

Output Drive Capability

Each output has a high/low drive option. The low drive option (slow slew rate) can be used to

reduce system noise by slowing down outputs that do not need to operate at maximum speed or

drive strength. Outputs default to high drive strength by Atmel software and can be set to low

drive strength through the slew rate option.

2.4

2.5

I/O Bank

The I/O pins of the ATF1508BE are grouped into two banks, Bank A and Bank B. Bank A com-

prises of I/O pins for macrocells 1 to 64 (Logic Block A, B, C, and D), and it is powered by

_CCIOA. Bank B comprises of I/O pins for macrocells 65 to 128 (Logic Block E, F, G, and H), and

it is powered by V_CCIOB

I/O Standard

The ATF1508BE supports a wide range of I/O standards which include LVTTL, LVCMOS33,

LVCMOS25, LVCMOS18 and LVCMOS15. The I/O pins of the ATF1508BE can also be individ-

ually configured to support SSTL-2 (Class I) and SSTL-3 (Class I) advanced I/O standards.

This and the two I/O banks, together, allow the ATF1508BE to be used for voltage level

translation.

3663A–PLD–1/08

1...6 7 8910 11 12...30

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