Datasheet > ATF1504ASV-15JI68

ATF1504ASV-15JI68

更新时间： 2024-01-08 13:59:08

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件
页数	文件大小	规格书
29页	312K
描述
Low-voltage, Complex Programmable Logic Device

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技术参数
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ATF1504ASV-15JI68 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	QCCJ, LDCC68,1.0SQ
针数：	68	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.75
其他特性：	YES	最大时钟频率：	100 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0	JTAG BST：	YES
长度：	24.2315 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	48
宏单元数：	64	端子数量：	68
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 48 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	2.5/3.3,3.3 V	可编程逻辑类型：	EE PLD
传播延迟：	15 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Programmable Logic Devices
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	24.2316 mm
Base Number Matches：	1

ATF1504ASV-15JI68 数据手册

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OR/XOR/CASCADE Logic

The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic.

Within a single macrocell, all the product terms can be routed to the OR gate, creating a

5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,

this can be expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic

functions. One input to the XOR comes from the OR sum term. The other XOR input can

be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level

input allows polarity selection. For registered functions, the fixed levels allow DeMorgan

minimization of product terms. The XOR gate is also used to emulate T- and JK-type

flip-flops.

Flip-flop

The ATF1504ASV(L)’s flip-flop has very flexible data and control functions. The data

input can come from either the XOR gate, from a separate product term or directly from

the I/O pin. Selecting the separate product term allows creation of a buried registered

feedback within a combinatorial output macrocell. (This feature is automatically imple-

mented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can

also be configured as a flow-through latch. In this mode, data passes through when the

clock is high and is latched when the clock is low.

The clock itself can either be one of the Global CLK Signal (GCK[0 : 2]) or an individual

product term. The flip-flop changes state on the clock’s rising edge. When the GCK sig-

nal is used as the clock, one of the macrocell product terms can be selected as a clock

enable. When the clock enable function is active and the enable signal (product term) is

low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be

either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic

OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product

term or always off.

Extra Feedback

I/O Control

The ATF1504ASV(L) macrocell output can be selected as registered or combinatorial.

The extra buried feedback signal can be either combinatorial or a registered signal

regardless of whether the output is combinatorial or registered. (This enhancement

function is automatically implemented by the fitter software.) Feedback of a buried com-

binatorial output allows the creation of a second latch within a macrocell.

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be

individually configured as an input, output or for bi-directional operation. The output

enable for each macrocell can be selected from the true or compliment of the two output

enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is

automatically done by the fitter software when the I/O is configured as an input, all mac-

rocell resources are still available, including the buried feedback, expander and cascade

logic.

Global Bus/Switch Matrix

Foldback Bus

The global bus contains all input and I/O pin signals as well as the buried feedback sig-

nal from all 64 macrocells. The switch matrix in each logic block receives as its inputs all

signals from the global bus. Under software control, up to 40 of these signals can be

selected as inputs to the logic block.

Each macrocell also generates a foldback product term. This signal goes to the regional

bus and is available to four macrocells. The foldback is an inverse polarity of one of the

macrocell’s product terms. The four foldback terms in each region allow generation of

high fan-in sum terms (up to nine product terms) with little additional delay.

ATF1504ASV(L)

1409I–PLD–2/03

1...3 4 567 8 9...29

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