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ATF1502AS PDF预览

ATF1502AS

更新时间: 2022-12-11 22:05:29
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器
页数 文件大小 规格书
18页 347K
描述
High Performance E2PROM CPLD

ATF1502AS 数据手册

 浏览型号ATF1502AS的Datasheet PDF文件第5页浏览型号ATF1502AS的Datasheet PDF文件第6页浏览型号ATF1502AS的Datasheet PDF文件第7页浏览型号ATF1502AS的Datasheet PDF文件第9页浏览型号ATF1502AS的Datasheet PDF文件第10页浏览型号ATF1502AS的Datasheet PDF文件第11页 
Absolute Maximum Ratings*  
*NOTICE:  
Stresses beyond those listed under “Absolute  
Maximum Ratings” may cause permanent dam-  
age to the device. This is a stress rating only and  
functional operation of the device at these or any  
other conditions beyond those indicated in the  
operational sections of this specification is not  
implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device  
reliability.  
Temperature Under Bias.................................. -40°C to +85°C  
Storage Temperature..................................... -65°C to +150°C  
Voltage on Any Pin with  
Respect to Ground .........................................-2.0V to +7.0V(1)  
Voltage on Input Pins  
with Respect to Ground  
During Programming.....................................-2.0V to +14.0V(1)  
Note:  
1. Minimum voltage is -0.6V DC, which may under-  
shoot to -2.0V for pulses of less than 20 ns. Max-  
imum output pin voltage is VCC + 0.75V DC,  
which may overshoot to 7.0V for pulses of less  
than 20 ns.  
Programming Voltage with  
Respect to Ground .......................................-2.0V to +14.0V(1)  
AC Characteristics  
-7  
-10  
-15  
-20  
-25  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Units  
Input or Feedback to  
Non-Registered Output  
tPD1  
7.5  
10  
3
15  
20  
25  
ns  
I/O Input or Feedback to  
Non-Registered Feedback  
tPD2  
7
9
3
12  
16  
25  
ns  
tSU  
tH  
Global Clock Setup Time  
Global Clock Hold Time  
6
0
7
0
11  
0
16  
0
20  
0
ns  
ns  
Global Clock Setup Time of  
Fast Input  
tFSU  
3
3
3
1
3
5
2
ns  
Global Clock Hold Time of  
Fast Input  
tFH  
0.5  
0.5  
1.5  
MHz  
tCOP  
tCH  
Global Clock to Output Delay  
Global Clock High Time  
Global Clock Low Time  
Array Clock Setup Time  
Array Clock Hold Time  
Array Clock Output Delay  
Array Clock High Time  
Array Clock Low Time  
4.5  
7.5  
5
8
10  
20  
13  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3
3
3
2
4
4
3
3
5
5
4
4
6
6
4
5
7
7
5
6
tCL  
tASU  
tAH  
tACOP  
tACH  
tACL  
tCNT  
10  
15  
3
3
4
4
6
6
8
8
10  
10  
Minimum Clock Global Period  
8
8
10  
10  
13  
13  
17  
17  
22  
22  
Maximum Internal Global  
Clock Frequency  
fCNT  
125  
125  
100  
100  
76.9  
76.9  
66  
66  
50  
50  
MHz  
ns  
tACNT  
fACNT  
Minimum Array Clock Period  
Maximum Internal Array  
Clock Frequency  
MHz  
ATF1502AS  
8

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