Datasheet > ATF1502AS-15AL44

ATF1502AS-15AL44

更新时间： 2022-12-02 00:14:03

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
26页	517K
描述
EE PLD, 15ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44

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ATF1502AS-15AL44 数据手册

Features

• High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

High-

performance

EEPROM CPLD

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

• Automatic 10 µA Standby for “L” Version

• Pin-controlled 1 mA Standby Mode

• Programmable Pin-keeper Inputs and I/Os

• Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-lead PLCC and TQFP

• Advanced EEPROM Technology

ATF1502AS

ATF1502ASL

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• Security Fuse Feature

• Green (Pb/Halide-fee/RoHS Compliant) Package Options

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

(“L” Versions)

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V_CCPower-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Input Transition Detection

– Power-down (“L” Versions)

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0995K–PLD–6/05

12 3 4 5 6 7...26

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