Datasheet > AT94K40AL-25DQU

AT94K40AL-25DQU

更新时间： 2024-01-31 06:56:38

品牌	Logo	应用领域
美国微芯 - MICROCHIP		时钟可编程逻辑
页数	文件大小	规格书
192页	1457K
描述
IC FPSLIC 40K GATE 25MHZ 208QFP

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中文翻译

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技术参数
数据手册

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AT94K40AL-25DQU 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	FQFP,
针数：	208	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.61	最大时钟频率：	18 MHz
CLB-Max的组合延迟：	3.4 ns	JESD-30 代码：	S-PQFP-G208
长度：	28 mm	可配置逻辑块数量：	2304
等效关口数量：	40000	端子数量：	208
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	2304 CLBS, 40000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	4.1 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	28 mm
Base Number Matches：	1

AT94K40AL-25DQU 数据手册

Features

• Monolithic Field Programmable System Level Integrated Circuit (FPSLIC^™)

– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR^®Core,

Extensive Data and Instruction SRAM and JTAG ICE

• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM^™

– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM

– High-performance DSP Optimized FPGA Core Cell

– Dynamically Reconfigurable In-System – FPGA Configuration Access Available

On-chip from AVR Microcontroller Core to Support Cache Logic^®Designs

– Very Low Static and Dynamic Power Consumption – Ideal for Portable and

Handheld Applications

• Patented AVR Enhanced RISC Architecture

– 120+ Powerful Instructions – Most Single Clock Cycle Execution

– High-performance Hardware Multiplier for DSP-based Systems

– Approaching 1 MIPS per MHz Performance

5K - 40K Gates

of AT40K FPGA

with 8-bit

Microcontroller,

up to 36K Bytes

of SRAM and

On-chip

– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers

– Low-power Idle, Power-save and Power-down Modes

– 100 µA Standby and Typical 2-3 mA per MHz Active

• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM

– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM

– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Extensive On-chip Debug Support

– Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)

• AVR Fixed Peripherals

– Industry-standard 2-wire Serial Interface

– Two Programmable Serial UARTs

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture

Modes and Dual 8-, 9- or 10-bit PWM

JTAG ICE

• Support for FPGA Custom Peripherals

– AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible

to FPGA

– FPGA Macro Library of Custom Peripherals

AT94KAL Series

Field

• 16 FPGA Supplied Internal Interrupts to AVR

• Up to Four External Interrupts to AVR

• 8 Global FPGA Clocks

Programmable

System Level

Integrated

Circuit

– Two FPGA Clocks Driven from AVR Logic

– FPGA Global Clock Access Available from FPGA Core

• Multiple Oscillator Circuits

– Programmable Watchdog Timer with On-chip Oscillator

– Oscillator to AVR Internal Clock Circuit

– Software-selectable Clock Frequency

– Oscillator to Timer/Counter for Real-time Clock

• V_CC: 3.0V - 3.6V

• 3.3V 33 MHz PCI-compliant FPGA I/O

– 20 mA Sink/Source High-performance I/O Structures

– All FPGA I/O Individually Programmable

• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process

• State-of-the-art Integrated PC-based Software Suite including Co-verification

• 5V I/O Tolerant

Rev. 1138G–FPSLI–11/03

12 3 4 5 6 7...192

中文翻译

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AT94S_05	ATMEL	获取价格	Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM an
AT94S05	ATMEL	获取价格	Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up to 36 Kbytes of SRAM and

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