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AT94K40AL-25BQU PDF预览

AT94K40AL-25BQU

更新时间: 2024-02-09 23:06:05
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
192页 1457K
描述
IC FPSLIC 40K GATE 25MHZ 144LQFP

AT94K40AL-25BQU 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFP包装说明:20 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MS-026 LQFP-144
针数:144Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.59
最大时钟频率:18 MHzCLB-Max的组合延迟:3.4 ns
JESD-30 代码:S-PQFP-G144JESD-609代码:e3
长度:20 mm湿度敏感等级:3
可配置逻辑块数量:2304等效关口数量:40000
端子数量:144最高工作温度:85 °C
最低工作温度:-40 °C组织:2304 CLBS, 40000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:20 mm

AT94K40AL-25BQU 数据手册

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Features  
Monolithic Field Programmable System Level Integrated Circuit (FPSLIC)  
AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core,  
Extensive Data and Instruction SRAM and JTAG ICE  
5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™  
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM  
– High-performance DSP Optimized FPGA Core Cell  
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available  
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs  
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and  
Handheld Applications  
Patented AVR Enhanced RISC Architecture  
– 120+ Powerful Instructions – Most Single Clock Cycle Execution  
– High-performance Hardware Multiplier for DSP-based Systems  
– Approaching 1 MIPS per MHz Performance  
5K - 40K Gates  
of AT40K FPGA  
with 8-bit  
Microcontroller,  
up to 36K Bytes  
of SRAM and  
On-chip  
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers  
– Low-power Idle, Power-save and Power-down Modes  
– 100 µA Standby and Typical 2-3 mA per MHz Active  
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM  
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM  
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM  
JTAG (IEEE std. 1149.1 Compliant) Interface  
– Extensive On-chip Debug Support  
– Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)  
AVR Fixed Peripherals  
– Industry-standard 2-wire Serial Interface  
– Two Programmable Serial UARTs  
– Two 8-bit Timer/Counters with Separate Prescaler and PWM  
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture  
Modes and Dual 8-, 9- or 10-bit PWM  
JTAG ICE  
Support for FPGA Custom Peripherals  
– AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible  
to FPGA  
– FPGA Macro Library of Custom Peripherals  
AT94KAL Series  
Field  
16 FPGA Supplied Internal Interrupts to AVR  
Up to Four External Interrupts to AVR  
8 Global FPGA Clocks  
Programmable  
System Level  
Integrated  
Circuit  
– Two FPGA Clocks Driven from AVR Logic  
– FPGA Global Clock Access Available from FPGA Core  
Multiple Oscillator Circuits  
– Programmable Watchdog Timer with On-chip Oscillator  
– Oscillator to AVR Internal Clock Circuit  
– Software-selectable Clock Frequency  
– Oscillator to Timer/Counter for Real-time Clock  
VCC: 3.0V - 3.6V  
3.3V 33 MHz PCI-compliant FPGA I/O  
– 20 mA Sink/Source High-performance I/O Structures  
– All FPGA I/O Individually Programmable  
High-performance, Low-power 0.35µ CMOS Five-layer Metal Process  
State-of-the-art Integrated PC-based Software Suite including Co-verification  
5V I/O Tolerant  
Rev. 1138G–FPSLI–11/03  
 

AT94K40AL-25BQU 替代型号

型号 品牌 替代类型 描述 数据表
AT94K40AL-25BQI ATMEL

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