Datasheet > AT80251G2D-SLRUM

AT80251G2D-SLRUM

更新时间： 2022-09-29 19:43:38

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
77页	1261K
描述
IC MCU 8BIT ROMLESS 44PLCC

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数据手册

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AT80251G2D-SLRUM 数据手册

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AT/TSC8x251G2D

Signals

Table 2. Product Name Signal Description

Signal

Name

Alternate

Function

Type Description

18^thAddress Bit

Output to memory as 18th external address bit (A17) in extended bus

applications, depending on the values of bits RD0 and RD1 in UCONFIG0

byte (see Table 13, Page 20).

A17

P1.7

P3.7

17^thAddress Bit

Output to memory as 17th external address bit (A16) in extended bus

applications, depending on the values of bits RD0 and RD1 in UCONFIG0

byte (see Table 13, Page 20).

A16

Address Lines

Upper address lines for the external bus.

A15:8⁽¹⁾

AD7:0⁽¹⁾

P2.7:0

P0.7:0

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

I/O

Address Latch Enable

ALE signals the start of an external bus cycle and indicates that valid

address information are available on lines A16/A17 and A7:0. An external

latch can use ALE to demultiplex the address from address/data bus.

ALE

–

Real-time Asynchronous Wait States Input

When this pin is active (low level), the memory cycle is stretched until it

becomes high. When using the Product Name as a pin-for-pin replacement

for a 8xC51 product, AWAIT# can be unconnected without loss of

compatibility or power consumption increase (on-chip pull-up).

AWAIT#

CEX4:0

–

Not available on DIP package.

PCA Input/Output pins

I/O CEXx are input signals for the PCA capture mode and output signals for

the PCA compare and PWM modes.

P1.7:3

External Access Enable

EA# directs program memory accesses to on-chip or off-chip code memory.

For EA# = 0, all program memory accesses are off-chip.

EA#

For EA# = 1, an access is on-chip ROM if the address is within the range of

the on-chip ROM; otherwise the access is off-chip. The value of EA# is

latched at reset.

–

For devices without ROM on-chip, EA# must be strapped to ground.

PCA External Clock input

ECI is the external clock input to the 16-bit PCA timer.

ECI

P1.2

P1.5

SPI Master Input Slave Output line

When SPI is in master mode, MISO receives data from the slave

peripheral. When SPI is in slave mode, MISO outputs data to the master

controller.

MISO

I/O

SPI Master Output Slave Input line

MOSI

I/O When SPI is in master mode, MOSI outputs data to the slave peripheral.

When SPI is in slave mode, MOSI receives data from the master controller.

P1.7

External Interrupts 0 and 1

INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the

TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#.

INT1:0#

P3.3:2

If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#.

4135F–8051–11/06

1...4 5 678 9 10...77

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