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AT697F-KG-E PDF预览

AT697F-KG-E

更新时间: 2024-02-23 16:32:29
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器和处理器外围集成电路uCs集成电路uPs集成电路异步传输模式ATM
页数 文件大小 规格书
155页 3140K
描述
Rad-Hard 32 bit SPARC V8 Processor

AT697F-KG-E 技术参数

生命周期:Active包装说明:FQFP,
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.6Is Samacsys:N
JESD-30 代码:S-PQFP-G256长度:37.085 mm
端子数量:256最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH认证状态:Not Qualified
座面最大高度:3.18 mm最大供电电压:1.95 V
最小供电电压:1.65 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:37.085 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

AT697F-KG-E 数据手册

 浏览型号AT697F-KG-E的Datasheet PDF文件第7页浏览型号AT697F-KG-E的Datasheet PDF文件第8页浏览型号AT697F-KG-E的Datasheet PDF文件第9页浏览型号AT697F-KG-E的Datasheet PDF文件第11页浏览型号AT697F-KG-E的Datasheet PDF文件第12页浏览型号AT697F-KG-E的Datasheet PDF文件第13页 
Pin Description  
ATMEL Convention  
‘*’ attached to a signal (e.g OE*) designate an active-low signal.  
When a bit of a register is writen in C-like style (e.g MCFG2JRAMWWS) it must be read as the  
RAMWWS bit in the register MCFG2.  
IU and FPU Signals  
A[27:0] - Address bus (output)  
A[27:0] bus carries the addresses during accesses to external memory. When access to cache  
memory is performed, the address of the last external memory access remains driven on the  
address bus.  
D[31:0] - Data bus (bi-directional)  
D[31:0] bus carries the data during accesses to memory. The processor automatically config-  
ures the bus as output and drive the lines during write transactions.  
During accesses to 8-bit areas, only D[31:24] are used.  
CB[7:0] - Check bits (bi-directional)  
CB[6:0] bus carries the EDAC checkbits during memory accesses. CB[7](1) takes the value of  
tcb[7] in the error control register. Processor only drives CB[7:0] during write transactions to  
areas programmed to be EDAC protected.  
Note:  
1. CB[7] is implemented to enable programming of flash memories. When only 7 bits are useful  
for EDAC protection, 8 are needed for programming.  
Memory Interface  
Signals  
General management  
OE* - Output enable (output)  
This active low output is asserted during read transactions on the memory bus.  
BRDY* - Bus ready (input)  
When driven low, this input indicates to the processor that the current memory access can be  
terminated on the next rising clock edge. When driven high, this input indicates to the processor  
that it must wait and not end the current access.  
READ - Read transaction (output)  
This active high output is asserted during read transactions on the memory bus.  
WRITE* - Write enable (output)  
This active low output provides a write strobe during write transactions on the memory bus.  
PROM  
SRAM  
ROMS*[1:0] - PROM chip-select (output)  
These active low outputs provide the chip-select signal for the PROM area. ROMS*[0] is  
asserted when the lower half of the PROM area is accessed (0 - 0x10000000), while ROMS*[1]  
is asserted for the upper half.  
RAMOE*[4:0] - RAM output enable (output)  
These active low signals provide an individual output enable for each RAM bank.  
RAMS*[4:0] - RAM chip-select (output)  
These active low outputs provide the chip-select signals for each RAM bank.  
RWE* [3:0] - RAM write enable (output)  
These active low outputs provide individual write strobes for each byte. RWEN[0] controls  
D[31:24], RWEN[1] controls D[23:16], etc.  
I/O  
IOS* - I/O select (output)  
10  
AT697F ADVANCE INFORMATION  
7703C–AERO–6/09  

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