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AT28HC256N PDF预览

AT28HC256N

更新时间: 2024-11-29 04:33:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
13页 230K
描述
256 (32K x 8) High-speed Parallel EEPROM

AT28HC256N 数据手册

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Features  
Fast Read Access Time – 90 ns  
Automatic Page Write Operation  
– Internal Address and Data Latches for 64 Bytes  
– Internal Control Timer  
Fast Write Cycle Times  
– Page Write Cycle Time: 3 ms Maximum  
– 1 to 64-byte Page Write Operation  
Low Power Dissipation: 300 µA Standby Current (CMOS)  
Hardware and Software Data Protection  
DATA Polling for End of Write Detection  
High Reliability CMOS Technology  
– Endurance: 105 Cycles  
– Data Retention: 10 Years  
Single 5V 10% Supply  
CMOS and TTL Compatible Inputs and Outputs  
JEDEC Approved Byte-wide Pinout  
256 (32K x 8)  
High-speed  
Parallel  
EEPROM  
Description  
The AT28HC256N is a high-performance electrically erasable and programmable read  
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-  
tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256N offers  
access times to 90 ns with power dissipation of just 440 mW. When the AT28HC256N  
is deselected, the standby current is less than 3 mA.  
AT28HC256N  
The AT28HC256N is accessed like a Static RAM for the read or write cycle without the  
need for external components. The device contains a 64-byte page register to allow  
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64  
bytes of data are internally latched, freeing the addresses and data bus for other oper-  
ations. Following the initiation of a write cycle, the device will automatically write the  
latched data using an internal control timer. The end of a write cycle can be detected  
by DATA Polling of I/O7. Once the end of a write cycle has been detected a new  
access for a read or write can begin.  
Atmel’s AT28HC256N has additional features to ensure high quality and manufactura-  
bility. The device utilizes internal error correction for extended endurance and  
improved data retention characteristics. An optional software data protection mecha-  
nism is available to guard against inadvertent writes. The device also includes an extra  
64 bytes of EEPROM for device identification or tracking.  
LCC, PLCC  
Top View  
Pin Configurations  
Pin Name  
A0 - A14  
CE  
Function  
Addresses  
A6  
A5  
A4  
A3  
A2  
5
6
7
8
9
29 A8  
28 A9  
27 A11  
26 NC  
25 OE  
24 A10  
23 CE  
22 I/O7  
21 I/O6  
Chip Enable  
Output Enable  
Write Enable  
Data Inputs/Outputs  
No Connect  
OE  
WE  
A1 10  
A0 11  
I/O0 - I/O7  
NC  
NC 12  
I/O0 13  
3446B–PEEPR–4/04  

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