Datasheet > AT28C256_08

AT28C256_08

更新时间： 2024-11-24 06:38:19

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
27页	649K
描述
256K (32K x 8) Paged Parallel EEPROM

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中文翻译

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数据手册

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AT28C256_08 数据手册

Features

• Fast Read Access Time – 150 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes

– Internal Control Timer

• Fast Write Cycle Times

– Page Write Cycle Time: 3 ms or 10 ms Maximum

– 1 to 64-byte Page Write Operation

• Low Power Dissipation

256K (32K x 8)

Paged Parallel

EEPROM

– 50 mA Active Current

– 200 µA CMOS Standby Current

• Hardware and Software Data Protection

• DATA Polling for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 10⁴or 10⁵Cycles

– Data Retention: 10 Years

AT28C256

• Single 5V 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• JEDEC Approved Byte-wide Pinout

• Full Military and Industrial Temperature Ranges

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT28C256 is a high-performance electrically erasable and programmable read-

only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-

tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access

times to 150 ns with power dissipation of just 440 mW. When the device is deselected,

the CMOS standby current is less than 200 µA.

The AT28C256 is accessed like a Static RAM for the read or write cycle without the

need for external components. The device contains a 64-byte page register to allow

writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to

64 bytes of data are internally latched, freeing the address and data bus for other

operations. Following the initiation of a write cycle, the device will automatically write

the latched data using an internal control timer. The end of a write cycle can be

detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a

new access for a read or write can begin.

Atmel’s AT28C256 has additional features to ensure high quality and manufacturabil-

ity. The device utilizes internal error correction for extended endurance and improved

data retention characteristics. An optional software data protection mechanism is

available to guard against inadvertent writes. The device also includes an extra

64 bytes of EEPROM for device identification or tracking.

0006K–PEEPR–01/08

12 3 4 5 6 7...27

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