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AT28C256-15JU-T PDF预览

AT28C256-15JU-T

更新时间: 2024-10-27 14:26:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数 文件大小 规格书
25页 530K
描述
IC EEPROM 256KBIT 150NS 32PLCC

AT28C256-15JU-T 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:QCCJ,Reach Compliance Code:compliant
风险等级:1.76Is Samacsys:N
最长访问时间:150 nsJESD-30 代码:R-PQCC-J32
JESD-609代码:e3长度:13.97 mm
内存密度:262144 bit内存集成电路类型:EEPROM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):245
编程电压:5 V座面最大高度:3.556 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:11.43 mm
最长写入周期时间 (tWC):10 msBase Number Matches:1

AT28C256-15JU-T 数据手册

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Features  
Fast Read Access Time – 150 ns  
Automatic Page Write Operation  
– Internal Address and Data Latches for 64 Bytes  
– Internal Control Timer  
Fast Write Cycle Times  
– Page Write Cycle Time: 3 ms or 10 ms Maximum  
– 1 to 64-byte Page Write Operation  
Low Power Dissipation  
256K (32K x 8)  
Paged Parallel  
EEPROM  
– 50 mA Active Current  
– 200 µA CMOS Standby Current  
Hardware and Software Data Protection  
DATA Polling for End of Write Detection  
High Reliability CMOS Technology  
– Endurance: 104 or 105 Cycles  
– Data Retention: 10 Years  
AT28C256  
Single 5V ± 10% Supply  
CMOS and TTL Compatible Inputs and Outputs  
JEDEC Approved Byte-wide Pinout  
Full Military and Industrial Temperature Ranges  
Green (Pb/Halide-free) Packaging Option  
1. Description  
The AT28C256 is a high-performance electrically erasable and programmable read-  
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-  
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access  
times to 150 ns with power dissipation of just 440 mW. When the device is deselected,  
the CMOS standby current is less than 200 µA.  
The AT28C256 is accessed like a Static RAM for the read or write cycle without the  
need for external components. The device contains a 64-byte page register to allow  
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to  
64 bytes of data are internally latched, freeing the address and data bus for other  
operations. Following the initiation of a write cycle, the device will automatically write  
the latched data using an internal control timer. The end of a write cycle can be  
detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a  
new access for a read or write can begin.  
Atmel’s AT28C256 has additional features to ensure high quality and manufacturabil-  
ity. The device utilizes internal error correction for extended endurance and improved  
data retention characteristics. An optional software data protection mechanism is  
available to guard against inadvertent writes. The device also includes an extra  
64 bytes of EEPROM for device identification or tracking.  
0006M–PEEPR–12/09  

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