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AT17LV128-10NL PDF预览

AT17LV128-10NL

更新时间: 2024-11-18 19:45:55
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟光电二极管内存集成电路
页数 文件大小 规格书
26页 616K
描述
Configuration Memory, 128KX1, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012AA, SOIC-8

AT17LV128-10NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.83其他特性:IT CAN OPERATES ON 4.75-5.25 RANGE SUPPLY VOLTAGE ALSO
最大时钟频率 (fCLK):10 MHzJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.925 mm
内存密度:131072 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:1
功能数量:1端子数量:8
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX1
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

AT17LV128-10NL 数据手册

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Features  
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,  
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration  
Programs for Field Programmable Gate Arrays (FPGAs)  
Supports both 3.3V and 5.0V Operating Voltage Applications  
In-System Programmable (ISP) via Two-Wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera® FLEX®, APEX™  
Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs  
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays  
Very Low-power CMOS EEPROM Process  
FPGA  
Configuration  
EEPROM  
Memory  
Programmable Reset Polarity  
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC  
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP  
Packages  
Emulation of Atmel’s AT24CXXX Serial EEPROMs  
Low-power Standby Mode  
High-reliability  
AT17LV65  
– Endurance: 100,000 Write Cycles  
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for  
Commercial Parts (at 70°C)  
Green (Pb/Halide-free/RoHS Compliant) Package Options Available  
AT17LV128  
AT17LV256  
AT17LV512  
AT17LV010  
AT17LV002  
AT17LV040  
1. Description  
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-  
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The  
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-  
lead PLCC, 20-lead SOIC and 44-lead TQFP, see Table 1-1. The AT17LV series  
Configurators uses a simple serial-access procedure to configure one or more FPGA  
devices. The user can select the polarity of the reset function by programming four  
EEPROM bytes. These devices also support a write-protection mechanism within its  
programming mode.  
3.3V and 5V  
System Support  
The AT17LV series configurators can be programmed with industry-standard pro-  
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.  
2321I–CNFG–2/08  

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