May 2007
rev 0.4
ASM3P623S01B/C/J
Timing-Safe™ Peak EMI reduction IC
General Features
available in 8pin package. The ASM3P623S01J is the
eight-pin version with crystal interface and accepts one
reference input and drives out two low-skew clocks.
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Clock distribution with Timing-Safe™ Peak EMI
Reduction
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Input frequency range: 20MHz - 50MHz
Zero input - output propagation delay
Low-skew outputs
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
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Output-output skew less than 250pS
Device-device skew less than 700pS
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Multiple ASM3P623S01B/C/J devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
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Less than 200pS cycle-to-cycle jitter
Available in 8pin, 150 mil SOIC, 4.4mm TSSOP
Packages (ASM3P623S00B/C/J)
3.3V operation
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Industrial temperature range
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
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Advanced 0.35µ CMOS technology
The First True Drop-in Solution
Functional Description
Refer “Spread Spectrum Control and Input-Output Skew
ASM3P623S01B/C/J is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed Timing-Safe™ clocks
with Peak EMI reduction. ASM3P623S01B/C accepts one
reference input and drives out three low-skew clocks. It is
Table”
for deviations and Input-Output Skew for
ASM3P623S01B/C/J devices
Block Diagram
VDD
SS%
SSON
PLL
Modulation
XIN/CLKIN
XOUT
Reference
Crystal
Feedforward
Phase
Loop
VCO
Feedback
CLKOUT
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.