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ASM3I623S05BF-08-TT

更新时间： 2024-11-25 06:38:11

品牌	Logo	应用领域
PULSECORE		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
15页	683K
描述
Timing-Safe™ Peak EMI reduction IC

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ASM3I623S05BF-08-TT 技术参数

生命周期：	Obsolete	包装说明：	4.40 MM, ROHS COMPLIANT, TSSOP-8
Reach Compliance Code：	unknown	风险等级：	5.84
系列：	23S	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	R-PDSO-G8	长度：	4.4 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	8
实输出次数：	4	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.25 ns	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	3 mm
最小 fmax：	50 MHz	Base Number Matches：	1

ASM3I623S05BF-08-TT 数据手册

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May 2007

rev 0.3

ASM3P623S05/09A/B

Timing-Safe™ Peak EMI reduction IC

General Features

the eight-pin version and accepts one reference input and

drives out five low-skew clocks.

•

Clock distribution with Timing-Safe™ Peak EMI

Reduction

All parts have on-chip PLLs that lock to an input clock on

the CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

•

Input frequency range: 20MHz - 50MHz

Zero input - output propagation delay

Low-skew outputs

• Output-output skew less than 250pS

• Device-device skew less than 700pS

Less than 200pS cycle-to-cycle jitter is compatible

with Pentium^®based systems

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(ASM3P623S09A/B), and in 8pin, 150 mil SOIC,

4.4mm TSSOP Packages (ASM3P623S05A/B)

3.3V Operation

Multiple ASM3P623S05/09A/B devices can accept the

same input clock and distribute it. In this case, the skew

between the outputs of the two devices is guaranteed to be

less than 700pS.

•

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than ±350pS, and the output-to-output skew is

guaranteed to be less than 250pS.

•

Advanced CMOS technology

The First True Drop-in Solution

Refer “Spread Spectrum Control and Input-Output Skew

Table” for deviations and Input-Output Skew for

ASM3P623S05A/B and ASM3P623S09A/B devices

Functional Description

ASM3P623S05/09A/B is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed Timing-Safe™ clocks

with Peak EMI Reduction. ASM3P623S09A/B accepts one

reference input and drives out nine low-skew clocks. It is

available in a 16pin Package. The ASM3P623S05A/B is

The ASM3P623S05A/B and ASM3P623S09A/B are

available in two different packages, as shown in the

ordering information table.

Block Diagram

PLL

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

PLL

CLKOUT

MUX

CLKIN

CLK1

CLK2

CLK3

ASM3P623S05A/B

CLK4

Select Input

Decoding

ASM3P623S09A/B

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...15

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ASM3I623S05BG-08-SR	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3I623S05BG-08-ST	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3I623S05BG-08-TR	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3I623S05BG-08-TT	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3I623S09AF-16-SR	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3I623S09AF-16-ST	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
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ASM3I623S09AF-16-TT	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
ASM3I623S09AG-16-SR	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
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