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ASM2P2351AH-24AT PDF预览

ASM2P2351AH-24AT

更新时间: 2024-11-08 03:01:39
品牌 Logo 应用领域
PULSECORE 光电二极管
页数 文件大小 规格书
13页 479K
描述
Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.209 INCH, SSOP-24

ASM2P2351AH-24AT 数据手册

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October 2005  
rev 0.2  
ASM2P2351AH  
1-Line To 10-Line Clock Driver With 3-State Outputs  
Product Description  
Features  
The ASM2P2351AH is a high-performance clock-driver  
circuit that distributes one input (A) to ten outputs (Y)  
with minimum skew for clock distribution. The output-  
enable (OE) input disables the outputs to a high-  
impedance state. Each output has an internal series  
damping resistor to improve signal integrity at the load.  
The ASM2P2351AH operates at nominal 3.3V Supply  
Voltage.  
Low Output Skew, Low Pulse Skew for Clock-  
Distribution and Clock-Generation Applications.  
Operates at 3.3V Supply Voltage.  
LVTTL-Compatible Inputs and Outputs.  
Supports Mixed-Mode Signal Operation.  
(5V Input and Output Voltages With 3.3V Supply  
Voltage).  
The propagation delays are adjusted at the factory  
using the P0 and P1 pins. The factory adjustments  
ensure that the part-to-part skew is minimized and is  
kept within a specified window. Pins P0 and P1 are not  
intended for customer use and should be connected to  
GND.  
Distributes One Clock Input to Ten Outputs.  
Outputs have Internal Series Damping Resistor  
to Reduce Transmission Line Effects.  
Distributed VCC and Ground Pins Reduce  
Switching Noise.  
Package Options Include Plastic Small-Outline  
and Shrink Small-Outline Packages.  
The ASM2P2351AH is characterized for operation  
from 0°C to 70°C.  
Logic Diagram (Positive Logic)  
5
OE  
23  
Y1  
21  
Y2  
19  
Y3  
18  
Y4  
6
A
16  
Y5  
7
8
PO P1  
14  
Y6  
11  
Y7  
9
Y8  
4
Y9  
2
Y10  
Alliance Semiconductor  
2575 Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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