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ASM2I3805A-20-SR PDF预览

ASM2I3805A-20-SR

更新时间: 2024-02-05 20:25:57
品牌 Logo 应用领域
PULSECORE 时钟驱动光电二极管时钟驱动器
页数 文件大小 规格书
13页 239K
描述
Low Skew Clock Driver, 3805 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.300 INCH, SOIC-20

ASM2I3805A-20-SR 技术参数

生命周期:Obsolete包装说明:0.209 INCH, SSOP-20
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:N系列:3805
输入调节:SCHMITT TRIGGERJESD-30 代码:R-PDSO-G20
长度:7.2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:2反相输出次数:
端子数量:20实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
传播延迟(tpd):5.2 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.6 ns座面最大高度:2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:5.3 mm
Base Number Matches:1

ASM2I3805A-20-SR 数据手册

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October 2005  
rev 0.2  
ASM2P3805A  
3.3V CMOS Buffer Clock Driver  
Functional Description  
Features  
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Advanced CMOS Technology  
The ASM2P3805A is a 3.3V, non-inverting clock driver built  
using advanced CMOS technology. The device consists of  
two banks of drivers, each with a 1:5 fanout and its own  
output enable control. The device has a "heartbeat" monitor  
for diagnostics and PLL driving. The MON output is  
identical to all other outputs and complies with the output  
specifications in this document. The ASM2P3805A offers  
low capacitance inputs.  
Guaranteed low skew < 500pS (max.)  
Very low duty cycle distortion < 1.0nS (max)  
Very low CMOS power levels  
TTL compatible inputs and outputs  
Inputs can be driven from 3.3V or 5V components  
Two independent output banks with 3-state control  
1:5 fanout per bank  
"Heartbeat" monitor output  
VCC = 3.3V ± 0.3V  
The ASM2P3805A is designed for high speed clock  
distribution where signal quality and skew are critical. The  
ASM2P3805A also allows single point-to-point transmission  
line driving in applications such as address distribution,  
where one signal must be distributed to multiple receivers  
with low skew and high signal quality.  
Available in SSOP, SOIC and QSOP Packages  
Block Diagram  
Pin Diagram  
VCCA  
OA1  
VCCB  
OB1  
1
2
20  
19  
OEA  
INA  
OA2  
OB2  
3
4
5
6
7
18  
17  
16  
5
OB3  
OA3  
OA1 – OA5  
GNDB  
GNDA  
OA4  
ASM2P3805A  
15 OB4  
14  
13  
OB5  
MON  
OEB  
INB  
OA5  
5
INB  
OB1 – OB5  
MON  
8
9
GNDQ  
OEA  
INA  
OEB  
12  
11  
10  
Alliance Semiconductor  
2575 Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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