Datasheet > AS8SLC512K32Q1-17/IT

AS8SLC512K32Q1-17/IT

更新时间： 2022-12-01 23:37:35

品牌	Logo	应用领域
MICROSS		静态存储器
页数	文件大小	规格书
12页	186K
描述
SRAM Module, 512KX32, 17ns, CMOS, CQFP68, CERAMIC, QFP-68

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AS8SLC512K32Q1-17/IT 数据手册

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SRAM

AS8SLC512K32

LOW POWER CHARACTERISTICS (L Version Only)

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

V_CCfor Retention Data

V_DR

All Inputs @ Vcc + 0.2V

or Vss + 0.2V,

V_CC= 2V

_CC= 3V

I_CCDR

Data Retention Current

CS\ = Vcc + 0.2V

Chip Deselect to Data

Retention Time

CDR

Operation Recovery Time

4, 11

LOW V_CCDATA RETENTION WAVEFORM

DATA RETENTION MODE

V_CC

4.5V

V_DR> 2V

^tCDR

^tR

V_DR

CS\ 1-4

NOTES

1. All voltages referenced to V_SS(GND).

2. Worst case address switching.

7. At any given temperature and voltage condition,

t_HZCS, is less than t_LZCS, and t_HZWEis less than t_LZWE

3. ICC is dependent on output loading and cycle rates.

8. WE\ is HIGH for READ cycle.

9. Device is continuously selected. Chip selects and output

enable are held in their active state.

HZ.

unloaded, and f=

RC(MIN)

10. Address valid prior to or coincident with latest

curring chip enable.

oc-

The speciﬁed value applies with the outputs

4. This parameter guaranteed but not tested.

5. Test conditions as speciﬁed with output loading as

shown in Fig. 1 & 2 unless otherwise noted.

6. t_HZCS, t_HZOEand t_HZWEare speciﬁed with C_L= 5pF as in

Fig. 2. Transition is measured +/- 200 mV typical from

steady state voltage, allowing for actual tester RC time

constant.

11. t_RC= READ cycle time.

12. Chip enable (CS\) and write enable (WE\) can initiate

and terminate a WRITE cycle.

13. I_CCis for full 32 bit mode.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS8SLC512K32

Rev. 2.6 01/10

1 2 3 456 7 8...12

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