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AS7C33128PFD18B-166TQI PDF预览

AS7C33128PFD18B-166TQI

更新时间: 2024-11-20 20:29:51
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
19页 538K
描述
Standard SRAM, 128KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C33128PFD18B-166TQI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.53
最长访问时间:3.5 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:2359296 bit
内存集成电路类型:STANDARD SRAM内存宽度:18
功能数量:1端子数量:100
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX18
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

AS7C33128PFD18B-166TQI 数据手册

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AS7C33128PFD18B  
February 2005  
®
3.3V 128K × 18 pipeline burst synchronous SRAM  
Features  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• Organization: 131,072 words × 18 bits  
• Fast clock speeds to 200 MHz  
• Fast clock to data access: 3.0/3.5/4.0 ns  
• Fast OE access time: 3.0/3.5/4.0 ns  
• Fully synchronous register-to-register operation  
• Double-cycle deselect  
• 2.5V or 3.3V I/O operation with separate V  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
DDQ  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Individual byte write and global write  
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CS  
CLR  
Burst logic  
128K × 18  
Memory  
array  
ADSC  
ADSP  
17  
Q
D
A[16:0]  
Address  
17  
CS  
15  
17  
register  
CLK  
18  
18  
GWE  
D
Q
DQb  
BW  
b
Byte Write  
registers  
CLK  
BWE  
BW  
D
Q
DQa  
2
Byte Write  
a
registers  
CLK  
CE0  
CE1  
OE  
Output  
registers  
D
Q
Q
Input  
registers  
Enable  
register  
CE2  
CE  
CLK  
CLK  
CLK  
D
Enable  
delay  
register  
Power  
down  
ZZ  
CLK  
OE  
18  
DQ [a,b]  
Selection guide  
–200  
5
–166  
–133  
7.5  
133  
4
Units  
Minimum cycle time  
6
ns  
MHz  
ns  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
200  
3.0  
375  
130  
30  
166  
3.5  
350  
100  
30  
325  
90  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
30  
1/31/05; v.1.2  
Alliance Semiconductor  
P. 1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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