Datasheet > 存储 > SRAM> AS7C31026-15JI

AS7C31026-15JI

更新时间： 2024-10-26 04:49:43

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
10页	239K
描述
5V / 3.3V 64KX16 CMOS SRAM

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中文翻译

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数据手册

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AS7C31026-15JI 数据手册

March 2001

AS7C1026

AS7C31026

5V/3.3V 64K×16 CMOS SRAM

• Low power consumption: STANDBY

Features

• AS7C1026 (5V version)

• AS7C31026 (3.3V version)

- 28 mW (AS7C1026) / max CMOS I/O

- 18 mW (AS7C31026) / max CMOS I/O

• 2.0V data retention

• Easy memory expansion with CE, OE inputs

• TTL-compatible, three-state I/O

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin 400 mil TSOP II

- 48-ball 6 mm × 8 mm CSP mBGA

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

• Industrial and commercial versions

• Organization: 65,536 words x 16 bits

• Center power and ground pins for low noise

• High speed

- 12/15/20 ns address access time

- 6,7,8 ns output enable access time

• Low power consumption: ACTIVE

- 880 mW (AS7C1026) / max @ 12 ns

- 396 mW (AS7C31026) / max @ 12 ns

Logic block diagram

Pin arrangement

44-Pin SOJ, TSOP II (400 mil)

V_CC

64K × 16

GND

48-CSP mini Ball-Grid-Array Package

Array

I/O15

I/O14

I/O13

I/O12

GND

V_CC

I/O11

I/O10

I/O9

I/O8

A10

A11

A₀

A₁

A₂

I/O0

I/O1

I/O2

I/O3

V_CC

GND

I/O4

I/O5

I/O6

I/O7

A15

A14

A13

A12

I/O8 UB

A4 CE I/O0

A6 I/O1 I/O2

A7 I/O3 V_DD

NC I/O4 V_SS

I/O0–I/O7

I/O8–I/O15

I/O

buffer

I/O9 I/O10 A5

V_SSI/O11 NC

V_DDI/O12 NC

Control circuit

Column decoder

F I/O14 I/O13 A14 A15 I/O5 I/O6

G I/O15 NC A12 A13 WE I/O7

A9 A10 A11 NC

Selection guide

AS7C1026-12

AS7C1026-15

AS7C1026-20

AS7C31026-12

AS7C31026-15

AS7C31026-20

Unit

Maximum address access time

Maximum output enable access time

AS7C1026

AS7C31026

AS7C1026

AS7C31026

160

110

150

100

140

Maximum operating current

Maximum CMOS standby current

Shaded areas indicate preliminary information.

3/23/01; v.1.0

Alliance Semiconductor

P. 1 of 10

12 3 4 5 6 7...10

中文翻译

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