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AS7C31024-15TJC PDF预览

AS7C31024-15TJC

更新时间： 2024-02-17 07:54:29
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
9页 199K
描述
5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)

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AS7C31024-15TJC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP32,.3
针数：32Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.72最长访问时间：15 ns
I/O 类型：COMMONJESD-30 代码：R-PDIP-T32
JESD-609代码：e0内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端口数量：1
端子数量：32字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX8输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP32,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.0005 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.07 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

AS7C31024-15TJC 数据手册

 浏览型号AS7C31024-15TJC的Datasheet PDF文件第1页浏览型号AS7C31024-15TJC的Datasheet PDF文件第3页浏览型号AS7C31024-15TJC的Datasheet PDF文件第4页浏览型号AS7C31024-15TJC的Datasheet PDF文件第5页浏览型号AS7C31024-15TJC的Datasheet PDF文件第6页浏览型号AS7C31024-15TJC的Datasheet PDF文件第7页 
AS7C1024  
AS7C31024  
®
Functional description  
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices  
organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple  
interfacing are desired.  
Equal address access and cycle times (tAA, tRC, tWC) of 10/ 12/ 15/ 20 ns with output enable access times (tOE) of 5/ 6/ 8/ 10 ns  
are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with  
multiple-bank systems.  
When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume I power.  
SB  
If the bus is static, then full standby power is reached (ISB1 or ISB2). For example, the AS7C31024 is guaranteed not to exceed  
0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.  
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/ O0-  
I/ O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid  
bus contention, external devices should drive I/ O pins only after outputshave been disabled with output enable ( OE) or write  
enable (WE).  
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.  
The chips drive I/ O pins with the data word referenced by the input address. When either chip enable is inactive, output  
enable is inactive, or write enable is active, output drivers stay in high-impedance mode.  
Absolute maximum ratings  
Parameter  
Symbol  
Min  
–0.50  
-0.50  
–0.50  
–
Max  
+7.0  
Unit  
V
AS7C1024  
V
t1  
Voltage on VCC relative to GND  
AS7C31024  
V
+5.0  
V
t1  
Voltage on any pin relative to GND  
Power dissipation  
V
VCC +0.50  
1.0  
V
t2  
PD  
W
Storage temperature (plastic)  
Ambient temperature with VCC applied  
DC current into outputs (low)  
Tstg  
–65  
–55  
–
+150  
+125  
20  
°C  
°C  
mA  
Tbias  
IOUT  
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect reliability.  
Truth table  
CE1  
H
X
L
CE2  
X
WE  
X
OE  
X
Data  
Mode  
High Z  
High Z  
High Z  
DOUT  
Standby (ISB, ISB1  
Standby (ISB, ISB1  
)
)
L
X
X
H
H
H
Output disable (ICC)  
Read (ICC)  
L
H
H
L
L
H
L
X
D
Write (ICC)  
IN  
Key: X = Don’t Care, L = Low, H = High  
2
ALLIANCE SEMICONDUCTOR  
11/ 29/ 00  
1234567...9

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