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AS4SD4M16 PDF预览

AS4SD4M16

更新时间: 2024-09-28 06:37:51
品牌 Logo 应用领域
AUSTIN 存储动态存储器
页数 文件大小 规格书
50页 1139K
描述
4 Meg x 16 SDRAM Synchronous DRAM Memory

AS4SD4M16 数据手册

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SDRAM  
AS4SD4M16  
Austin Semiconductor, Inc.  
4 Meg x 16 SDRAM  
PIN ASSIGNMENT  
Synchronous DRAM Memory  
(Top View)  
FEATURES  
54-PinTSOP  
Extended Testing Over -55°C to +125° C and  
Industrial Temp -40°C to 85° C  
WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK  
Fully synchronous; all signals registered on positive  
edge of system clock  
Internal pipelined operation; column address can be  
changed every clock cycle  
Internal banks for hiding row access/precharge  
Programmable burst lengths: 1, 2, 4, 8 or full page  
Auto Precharge and Auto Refresh Modes  
Self Refresh Mode (Industrial, -40°C to 85° C only)  
4,096-cycle refresh  
LVTTL-compatible inputs and outputs  
Single +3.3V ±0.3V power supply  
Longer lead TSOP for improved reliability  
(OCPL*)  
Short Flow / Long Flow Test Screening Options  
OPTIONS  
MARKING  
Configurations  
4 Meg x 16 (1 Meg x 16 x 4 banks)  
Plastic Package - OCPL*  
4M16  
54-pin TSOP (400 mil)  
DG  
No. 901  
Timing (Cycle Time)  
8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns)  
10ns; tAC = 9ns @ CL = 2  
Note: “\” indicates an active low.  
-8  
-10  
4 Meg x 16  
1 Meg x 16 x 4 banks  
Configuration  
Operating Temperature Ranges  
-Military (-55°C to +125° C)  
-Industrial Temp (-40°C to 85° C)  
Refresh Count  
4K  
XT  
IT  
Row Addressing  
Bank Addressing  
Column Addressing  
4K (A0-A11)  
4 (BA0, BA1)  
256 (A0-A7)  
KEY TIMING PARAMETERS  
SPEED  
CLOCK  
ACCESS TIME  
SETUP  
TIME  
2ns  
3ns  
2ns  
HOLD  
TIME  
1ns  
1ns  
1ns  
GRADE FREQUENCY CL = 2** CL = 3**  
-8  
-10  
-8  
125 MHz  
100 MHz  
83 MHz  
66 MHz  
9ns  
9ns  
6.5ns  
7ns  
For more products and information  
please visit our web site at  
-10  
3ns  
1ns  
www.austinsemiconductor.com  
*Off-center parting line  
**CL = CAS (READ) latency  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD4M16  
Rev. 1.5 10/01  
1

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