Datasheet > AS4LC4M16S0

AS4LC4M16S0

更新时间： 2022-11-26 04:37:58

品牌	Logo	应用领域
ALSC		动态存储器
页数	文件大小	规格书
24页	548K
描述
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

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AS4LC4M16S0 数据手册

AS4LC8M8S0

AS4LC4M16S0

specifications and conditions

(0° C ≤ T ≤ 70° C, V , V

= +3.3V ± 0.3V)

DD DDQ

Max

–8

Parameter

Operating current: active mode; burst = 2; READ or WRITE;

_RC= t_RC(min); CAS latency = 3

Symbol

I_DD1

–75

115

–10F/ 10 Units Notes

4, 5

4,5

Standby current: power-down mode; all banks idle;

CKE = low

I_DD2

I_DD3

I_DD4

I_DD5

Standby current: active mode; CKE = high; CS# = high; all

banks active after t_RCDmet; no accesses in progress

4, 5

4,5

Operating current: burst mode; continuous burst; READ or

WRITE; all banks active; CAS latency = 3

140

210

130

210

120

190

t_RFC= t_RFC(min);

4, 5

CL = 3

Auto refresh current: CKE = high;

CS# = high

t_RFC= 15.625ms;

CL = 3

I_DD6

I_DD7

4,5

Self-refresh current: CKE ≤ 0.2V

Notes

specifications are tested after proper initialization of the device.

is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open.

tests have V = 0V and V = 3V.

IL IH

current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time.

Address transitions average one transition every two clock cycles.

7/ 5/ 00

ALLIANCE SEMICONDUCTOR

1...4 5 678 9 10...24

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