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AS4LC4M16S0 PDF预览

AS4LC4M16S0

更新时间： 2022-11-26 04:37:58
品牌 Logo 应用领域
ALSC 动态存储器
页数 文件大小 规格书
24页 548K
描述
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

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AS4LC4M16S0 数据手册

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AS4LC4M16S0  
AS4LC16M4S0  
®
Commands  
BA0/  
CKE CS RAS CAS WE DQM BA1 A10 A9–A0  
Command  
CKE  
DQ Note  
n-1  
n
Register Mode register set  
Auto refresh  
H*  
H
H
L
L
L
L
L
H
L
L
L
L
H
X
L
L
L
L
H
H
H
X
H
X
X
X
X
X
X
Op code  
–
X
1,2  
3
H
–
–
Entry  
H
L
–
3
Refresh  
X
–
X
Self  
H
X
H
–
3
refresh  
Exit  
L
H
H
H
H
H
–
–
3
Bank activate  
V
row address  
X
X
Auto precharge disable  
Auto precharge enable  
Auto precharge disable  
Auto precharge enable  
L
H
L
4
4,5  
4
column  
address  
Read  
L
H
L
H
X
V
V
column  
address  
Write  
H
H
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
Valid  
Active  
X
H
4,5  
6
Burst stop  
Precharge  
X
Selected bank  
All banks  
V
X
L
X
X
4
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
Exit  
H
L
L
H
L
Clock suspend or  
active power down  
X
X
X
X
X
X
H
L
Entry  
H
Precharge power  
down mode  
X
X
X
X
X
X
X
X
H
L
Exit  
L
H
H
H
H
X
Write enable/ output  
enable  
X
X
X
X
7
DQM  
H
Write inhibit/ Output  
High-Z  
H
L
X
H
X
H
X
H
X
X
No operation command  
X
X
X
X
1
OP = operation code.  
A0~A11 and BA0~BA1 program keys.  
2
3
MRS can be issued only when all banks are precharged. A new command can be issued 1 clock cycle after MRS.  
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.  
Auto/ self refresh can only be issued after all banks are precharged.  
BA0~BA1: bank select addresses.  
4
If A10/ AP is High at row precharge, BA0 and BA1 are ignored and all banks are selected.  
During read, write, row active, and prechage:  
If BA0 and BA1 are Low, Bank A is selected.  
If BA0 = Low and BA1 = High, Bank B is selected.  
If BA0 = High and BA1 = Low, Bank C is selected.  
If BA0 and BA1 are High, Bank D is selected.  
5
A new read/ write command to the same bank cannot be issued during a burst read/ write with auto precharge.  
A new row active command can be issued after t(t / t + BL +) cycles.  
RP CK  
6
7
Burst stop command valid at every burst length.  
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).  
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).  
4
ALLIANCE SEMICONDUCTOR  
7/ 5/ 00  
1234567...24

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