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AS4C1M16F5-60TI PDF预览

AS4C1M16F5-60TI

更新时间： 2024-02-01 13:38:54
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
21页 475K
描述
5V 1M X 16 CMOS DRAM

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AS4C1M16F5-60TI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2, TSOP44/50,.46,32
针数：50Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.78访问模式：FAST PAGE
最长访问时间：60 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e0长度：20.95 mm
内存密度：16777216 bit内存集成电路类型：FAST PAGE DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：44
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44/50,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：240电源：5 V
认证状态：Not Qualified刷新周期：1024
座面最大高度：1.2 mm自我刷新：NO
最大待机电流：0.002 A子类别：DRAMs
最大压摆率：0.135 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10.16 mmBase Number Matches：1

AS4C1M16F5-60TI 数据手册

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AS4C1M16F5  
®
Notes  
1
2
3
I
, I , and I  
are dependent on frequency.  
CC1 CC3  
CC4  
I
and I  
depend on output loading. Specified values are obtained with the output open.  
CC1  
CC4  
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal  
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after  
extended periods of bias without clocks (greater than 8 ms).  
4
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) ≥ GND and V  
IH  
T
IL  
(max) ≤ V  
.
CC  
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .  
IH  
IL  
IH  
IL  
Operation within the t  
(max) limit insures that t  
(max) can be met. t  
(max) is specified as a reference point only. If t  
is greater than the  
RCD  
RAC  
RCD  
RCD  
specified t  
(max) limit, then access time is controlled exclusively by t  
.
CAC  
RCD  
7
Operation within the t  
(max) limit insures that t  
(max) can be met. t (max) is specified as a reference point only. If t  
RAD  
is greater than the  
RAD  
RAC  
RAD  
specified t  
(max) limit, then access time is controlled exclusively by t .  
AA  
RAD  
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).  
Either t or t must be satisfied for a read cycle.  
9
RCH  
RRH  
10  
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t  
is referenced from  
OFF  
OFF  
rising edge of RAS or CAS, whichever occurs last.  
t , t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.  
WCS WCH RWD CWD  
11  
AWD  
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the  
WS  
WH  
cycle. If tRWD ≥ t  
(min), t  
≥ t  
(min) and tAWD ≥ t  
(min), the cycle is a read-write cycle and the data out will contain data read from the  
RWD  
CWD  
CWD  
AWD  
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.  
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.  
13 Access time is determined by the longest of t or t or t  
CAA  
CAC  
CPA  
14  
tASC ≥ t to achieve t (min) and t (max) values.  
CP PC CPA  
15 These parameters are sampled and not 100% tested.  
16 These characteristics apply to AS4C1M16F5 5V devices.  
AC test conditions  
- Access times are measured with output reference levels  
of VOH = 2.4V and VOL = 0.4V,  
+5V  
V
IH = 2.4V and VIL = 0.8V  
R1 = 828Ω  
- Input rise and fall times: 2 ns  
Dout  
100 pF*  
R2 = 295Ω  
*including scope  
and jig capacitance  
GND  
Figure A: Equivalent output load  
Falling input  
Key to switching waveforms  
Rising input  
Undefined output/don’t care  
4/11/01; v.0.9.1  
Alliance Semiconductor  
P. 7 of 21  
1...45678910...21

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