AS42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
256K x 4 DRAM
WITH 512 x 4 SAM
PIN ASSIGNMENT (Top View)
VRAM
AVAILABLE AS MILITARY
SPECIFICATION
MIL-STD-883
28-Pin DIP
(400 MIL)
28-Pin SOJ
28-Pin LCC
FEATURES
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SC
SDQ1
SDQ2
TR\-OE\
DQ1
DQ2
ME\-WE\
NC
1
2
3
4
5
6
7
8
Industry standard pinout, timing and functions
High-performance, CMOS silicon-gate process
Single +5V ±10% power supply
SC
SDQ1
SDQ2
TR\-OE\
DQ1
DQ2
ME\-WE\
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
2
3
4
5
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
Inputs and outputs are fully TTL compatible
Refresh modes:RAS\ ONLY, CAS\-BEFORE-RAS\ (CBR)
and HIDDEN
6
7
8
9
512-cycle refresh within 8ms
RAS\
A8
A6
A5
A4
RAS\
A8
A6
A5
A4
9
Optional FAST PAGE MODE access cycles
Dual port organization: 256K x 4 DRAM port
512 x 4 SAM port
No refresh required for serial access memory
Low power: 15mW standby; 275mW active, typical
10
11
12
13
14
10
11
12
13
14
VCC
VCC
SPECIAL FUNCTIONS
28-Pin DIP
(F-12)
JEDEC Standard Function set
PERSISTENT MASKED WRITE
SPLIT READ TRANSFER
VSS
SC
1
2
3
4
5
6
7
8
9
28
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
SDQ1
SDQ2
TR\-OE\
DQ1
DQ2
ME\-WE\
NC
27
26
25
24
23
22
21
20
19
18
17
16
15
WRITE TRANSFER/SERIAL INPUT
ALTERNATE WRITE TRANSFER
BLOCK WRITE
OPTIONS
MARKING
RAS\
A8
A6
A5
A4
Timing [DRAM, SAM (cycle/access)]
100ns, 30ns/27ns
10
11
12
13
14
-10
-12
120ns, 35ns/35ns
80ns, 30ns/25ns
-8
VCC
Packages
Ceramic SOJ
Ceramic DIP (400 mil)
Ceramic LCC
DCJ
C
EC
F
No. 500
No. 109
No. 203
No. 302
Ceramic Flat Pack
GENERALDESCRIPTION
The AS42C4256 883C is a high-speed, dual port CMOS
dynamic random access memory or video RAM (VRAM) containing
1,048,576 bits. These bits may be accessed by a 4-bit wide DRAM
port or a 512 x 4-bit serial access memory (SAM) port. Data may
be transferred bidirectionally between the DRAM and the SAM.
The DRAM portion of the VRAM is functionally identical to
the AS4C4256 (256K x 4 DRAM). Four 512-bit data registers make
up the SAM portion of the VRAM. Data I/O and internal data
transfer are accomplished using three separate bidirectional data
paths; the 4-bit random access I/O port, the four internal 512 bit
wide paths between the DRAM and the SAM, and the 4-bit serial I/O
port for the SAM. The rest of the circuitry consists of the control,
timing and address decoding logic. Each port may be operated
asynchronously and independently of the other except when data is
being transferred
AS42C4256 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
3-27