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AS29F400T-70SI PDF预览

AS29F400T-70SI

更新时间: 2024-11-23 17:14:35
品牌 Logo 应用领域
ALSC 光电二极管内存集成电路
页数 文件大小 规格书
20页 444K
描述
Flash, 512KX8, 70ns, PDSO44, 0.600 INCH, SO-44

AS29F400T-70SI 数据手册

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High Performance  
AS29F400  
512K×8/256K×16  
5V CMOS Flash EEPROM  
®
512K×8/256K×16 CMOS Flash EEPROM  
Preliminary information  
Features  
• Organization: 512K×8 or 256K×16  
• Low power consumption  
- 35 mA maximum read current  
- 60 mA maximum program current  
- 1 µA typical standby current (RESET = 0)  
• JEDEC standard software, packages and pinouts  
- 48-pin TSOP  
• Sector architecture  
- One 16K; two 8K; one 32K; and seven 64K byte sectors  
- Boot code sector architecture—T (top) or B (bottom)  
- Erase any combination of sectors or full chip  
• Single 5.0±0.5V power supply for read/write operations  
• Sector protection  
- 44-pin SO  
• Detection of program/erase cycle completion  
- DQ7 DATA polling  
- DQ6 toggle bit  
- RY/BY output  
• Erase suspend/resume  
• High speed 55/70/90/120/150 ns address access time  
• Automated on-chip programming algorithm  
- Automatically programs/verifies data at specified address  
• Automated on-chip erase algorithm  
- Automatically preprograms/erases chip or specified sectors  
- Supports reading data from or programming data to a sector  
not being erased  
• 10,000 write/erase cycle endurance  
• Hardware RESET pin  
- Resets internal state machine to read mode  
• Low V write lock-out below 3.2V  
CC  
Logic block diagram  
Pin arrangement  
48-pin TSOP  
44-pin SO  
Sector protect  
switches  
RY/BY  
DQ0–DQ15  
V
CC  
NC  
RY/BY  
A17  
A7  
1
44  
RESET  
WE  
V
SS  
2
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
Erase voltage  
generator  
Input/output  
buffers  
3
A8  
RESET  
4
A9  
A6  
5
A10  
Program/erase  
control  
A5  
6
A11  
WE  
BYTE  
A4  
7
A12  
A3  
8
A13  
Program voltage  
generator  
Command  
register  
A2  
9
A14  
AS29F400  
A1  
A0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A15  
A16  
STB  
Chip enable  
Output enable  
Logic  
Data latch  
CE  
BYTE  
VSS  
CE  
OE  
A-1  
VSS  
OE  
DQ15/A-1  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
VCC  
DQ0  
DQ8  
DQ1  
DQ9  
DQ2  
DQ10  
DQ3  
DQ11  
Y decoder  
Y gating  
STB  
V
detector  
Timer  
CC  
X decoder  
Cell matrix  
A0–A17  
Selection guide  
29F400-55 29F400-70 29F400-90 29F400-120 29F400-150 Unit  
Maximum access time  
t
t
t
55  
55  
25  
70  
70  
30  
90  
90  
35  
120  
120  
50  
150  
150  
55  
ns  
ns  
ns  
AA  
CE  
OE  
Maximum chip enable access time  
Maximum output enable access time  
ALLIANCE SEMICONDUCTOR  
1

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