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AS29F040DCG-150/XT PDF预览

AS29F040DCG-150/XT

更新时间： 2024-01-29 04:51:09
品牌 Logo 应用领域
AUSTIN /
页数 文件大小 规格书
27页 1428K
描述
512K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY

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AS29F040DCG-150/XT 技术参数

是否Rohs认证： 不符合生命周期：Active
零件包装代码：SOIC包装说明：SOP, SOP32,.5
针数：32Reach Compliance Code：compliant
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.51
风险等级：5.39最长访问时间：150 ns
命令用户界面：YES数据轮询：YES
耐久性：1000000 Write/Erase CyclesJESD-30 代码：R-XDSO-G32
长度：20.828 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1部门数/规模：8
端子数量：32字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：512KX8封装主体材料：UNSPECIFIED
封装代码：SOP封装等效代码：SOP32,.5
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V编程电压：5 V
认证状态：Not Qualified座面最大高度：3.3528 mm
部门规模：64K最大待机电流：0.000005 A
子类别：Flash Memories最大压摆率：0.04 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
切换位：YES类型：NOR TYPE
宽度：10.414 mmBase Number Matches：1

AS29F040DCG-150/XT 数据手册

 浏览型号AS29F040DCG-150/XT的Datasheet PDF文件第4页浏览型号AS29F040DCG-150/XT的Datasheet PDF文件第5页浏览型号AS29F040DCG-150/XT的Datasheet PDF文件第6页浏览型号AS29F040DCG-150/XT的Datasheet PDF文件第8页浏览型号AS29F040DCG-150/XT的Datasheet PDF文件第9页浏览型号AS29F040DCG-150/XT的Datasheet PDF文件第10页 
FLASH  
AS29F040  
Austin Semiconductor, Inc.  
If DQ5 goes high during a program or erase operation,  
writing the reset command returns the device to reading array  
data (also applies during Erase Suspend).  
Chip Erase Command Sequence  
Chip erase is a six-bus-cycle operation. The chip erase  
command sequence is initiated by writing two unlock cycles,  
followed by a set-up command. Two additional unlock write  
cycles are then followed by the chip erase command, which in  
Autoselect Command Sequence  
The autoselect command sequence allows the host turn invokes the Embedded Erase algorithm. The device does  
system to access the manufacturer and devices codes, and not require the system to preprogram prior to erase. The  
determine whether or not a sector is protected. The Command Embedded Erase algorithm automatically preprograms and  
Definitions table shows the address and data requirements. verifies the entire memory for an all zero data pattern prior to  
This method is an alternative to that shown in the Autoselect electrical erase. The system is not required to provide any  
Codes (High Voltage Method) table, which is intended for controls or timings during these operations. The Command  
Definitions table shows the address and data requirements for  
the chip erase command sequence.  
Any commands written to the chip during the Embedded  
Erase algorithm are ignored.  
The system can determine the status of the erase  
operation by using DQ7, DQ6, or DQ2. See “Write Operation  
Status” for information on these status bits. When the  
Embedded Erase algorithm is complete, the device returns to  
reading array data and addresses are no longer latched.  
Figure 2 illustrates the algorithm for the erase operation.  
See the Erase/Program Operations tables in “AC  
Characteristics” for parameters, and the Chip /Sector Erase  
Operation Timings for timing waveforms.  
PROM programmers and requires VID on address bit A9.  
The auto select command sequence is initiated by writing  
two unlock cycles, followed by the autoselect command. The  
device then enters the autoselect mode, and the system may  
read at any address any number of times, without initiating  
another command sequence.  
A read cycle at address XX00h retrieves the manufacturer  
code. A read cycle at address XX01h returns the device code.  
A read cycle containing a sector address (SA) and the address  
02h in returns 01h if that sector is protected, or 00h if it is  
unprotected. Refer to the Sector Address tables for valid sector  
addresses.  
The system must write the reset command to exit the  
autoselect mode and return to reading array data.  
FIGURE 1: PROGRAM OPERATION  
Byte Program Command Sequence  
Programming is a four-bus-cycle operation. The program  
command sequence is initiated by writing two unlock write  
cycles, followed by the program set-up command. The  
program address and data are written next, which in turn initiate  
the Embedded Program algorithm. The system is not required  
to provide further controls or timings. The device  
automatically provides internally generated program pulses and  
verify the programmed cell margin. The Command Definitions  
take shows the address and data requirements for the byte  
program command sequence.  
When the Embedded Program algorithm is complete, the  
device then returns to reading array data and addresses are no  
longer latched. The system can determine the status of the  
program operation by using DQ7 or DQ6. See “Write Operation  
Status” for information on these status bits.  
Any commands written to the device during the  
Embedded Program Algorithm are ignored.  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed from a “0”  
back to a “1”. Attempting to do so may halt the operation and  
set DQ5 to “1”, or cause the Data\ Polling algorithm to indicate  
the operation was successful. However, a succeeding read will  
show that the data is still “0”. Only erase operations can  
convert a “0” to a “1”.  
NOTE: See the appropriate Command Definitions table for program  
command sequence.  
AS29F040  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
Rev. 2.2 09/07  
7
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