Datasheet > AS29F040DCG-150/XT

AS29F040DCG-150/XT

更新时间： 2024-01-18 16:41:03

品牌	Logo	应用领域
AUSTIN		/
页数	文件大小	规格书
27页	1428K
描述
512K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY

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技术参数
数据手册

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AS29F040DCG-150/XT 技术参数

是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	SOIC	包装说明：	SOP, SOP32,.5
针数：	32	Reach Compliance Code：	compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.32.00.51
风险等级：	5.39	最长访问时间：	150 ns
命令用户界面：	YES	数据轮询：	YES
耐久性：	1000000 Write/Erase Cycles	JESD-30 代码：	R-XDSO-G32
长度：	20.828 mm	内存密度：	4194304 bit
内存集成电路类型：	FLASH	内存宽度：	8
功能数量：	1	部门数/规模：	8
端子数量：	32	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	512KX8	封装主体材料：	UNSPECIFIED
封装代码：	SOP	封装等效代码：	SOP32,.5
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	编程电压：	5 V
认证状态：	Not Qualified	座面最大高度：	3.3528 mm
部门规模：	64K	最大待机电流：	0.000005 A
子类别：	Flash Memories	最大压摆率：	0.04 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
切换位：	YES	类型：	NOR TYPE
宽度：	10.414 mm	Base Number Matches：	1

AS29F040DCG-150/XT 数据手册

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FLASH

AS29F040

Austin Semiconductor, Inc.

power-down. The command register and all internal program/ The device is also ready to read array data after completing an

erase circuits are disabled, and the device resets. Subsequent Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the

device enters the Erase Suspend mode. The system can read

array data using the standard read timings, except that if it

reads at an address within erase-suspended sectors, the device

outputs status data. After completing a programming

operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See “Erase

Suspend/Erase Resume” for more information.

writes are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control pins to prevent

unintentional writes when V_CCis greater than V_LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\

do not initiate a write cycle.

The system must issue the reset command to re-enable the

device for reading array data if DQ5 goes high, or while in the

autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information. The

Read Operations table provides the read parameters, and the

Read Operation Timings diagram shows the timing diagram.

Logical Inhibit

Write cycles are inhibited by holding any one of OE\ = V_IL,

CE\ = V_IHor WE\ = V_IH. To initiate a write cycle, CE\ and WE\

must be a logical zero while OE\ is a logical one.

Power-Up Write Inhibit

If WE\ = CE\ = V_ILand OE\ = V_IHduring power up, the

device does not accept commands on the rising edge of WE\.

The internal state machine is automatically reset to reading

array data on power-up.

Reset Command

Writing the reset command to the device resets the device

to reading array data. Address bits are don’t care for this

command.

The reset command may be written between the sequence

cycles in an erase command sequence before erasing begins.

COMMAND DEFINITIONS

Writing specific address and data commands or sequences This resets the device to reading array data. Once erasure

into the command register initiates device operations. The begins, however, the device ignores reset commands until the

Command Definitions table defines the valid register command operation is complete.

sequences. Writing incorrect address and data values or

writing them in the improper sequence resets the device to cycles in a program command sequence before programming

reading array data. begins. This resets the device to reading array data (also applies

The reset command may be written between the sequence

All addresses are latched on the falling edge of WE\ or to programming in Erase Suspend Mode). Once programming

CE\, whichever happens later. All data is latched on the rising begins, however, the device ignores reset commands until the

edge of WE\ or CE\, whichever happens first. Refer to the operation is complete.

appropriate timing diagrams in the “AC Characteristics”

section.

Reading Array Data

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve data.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to return

to reading array data (also applies to autoselect during Erase

Suspend).

TABLE 3: Autoselect Codes (High Voltage Method)

Identifier Code

On DQ7 to DQ0

Description

A18 - A16 A15 - A10 A9

A8 - A7

A5 - A2

Manufacturer ID

Device ID

01h

A4h

01h (protected)

Sector Protection

Verification

Sector

Address

00h

(unprotected)

AS29F040

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 2.2 09/07

1...3 4 567 8 9...27

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AS29F040DCG-55/Q	AUSTIN	512K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY	获取价格
AS29F040DCG-55/XT	AUSTIN	512K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY	获取价格
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