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AS29F040CW-70/883C PDF预览

AS29F040CW-70/883C

更新时间： 2024-02-17 04:09:48
品牌 Logo 应用领域
AUSTIN 内存集成电路
页数 文件大小 规格书
27页 1428K
描述
512K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY

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AS29F040CW-70/883C 技术参数

是否Rohs认证： 不符合生命周期：Active
零件包装代码：DIP包装说明：DIP, DIP32,.6
针数：32Reach Compliance Code：compliant
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.51
风险等级：5.39Is Samacsys：N
最长访问时间：70 ns命令用户界面：YES
数据轮询：YES耐久性：1000000 Write/Erase Cycles
JESD-30 代码：R-CDIP-T32长度：42.418 mm
内存密度：4194304 bit内存集成电路类型：FLASH
内存宽度：8功能数量：1
部门数/规模：8端子数量：32
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：512KX8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP32,.6封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
编程电压：5 V认证状态：Not Qualified
筛选级别：MIL-STD-883座面最大高度：5.08 mm
部门规模：64K最大待机电流：0.000005 A
子类别：Flash Memories最大压摆率：0.04 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
切换位：YES类型：NOR TYPE
宽度：15.24 mmBase Number Matches：1

AS29F040CW-70/883C 数据手册

 浏览型号AS29F040CW-70/883C的Datasheet PDF文件第5页浏览型号AS29F040CW-70/883C的Datasheet PDF文件第6页浏览型号AS29F040CW-70/883C的Datasheet PDF文件第7页浏览型号AS29F040CW-70/883C的Datasheet PDF文件第9页浏览型号AS29F040CW-70/883C的Datasheet PDF文件第10页浏览型号AS29F040CW-70/883C的Datasheet PDF文件第11页 
FLASH  
AS29F040  
Austin Semiconductor, Inc.  
including the 50µs time-out period during the sector erase  
command sequence. The Erase Suspend command is ignored if  
written during the chip erase operation or Embedded Program  
algorithm. Writing the Erase Suspect command during the  
Sector Erase time-out immediately terminates the time-out  
period and suspends the erase operation. Addresses are “don’t  
cares” when writing the Erase Suspect command.  
When the Erase Suspect command is written during a  
sector erase operation, the device requires a maximum of 20µs  
to suspend the erase operation. However, when the Erase  
Suspend command is written during the sector erase time-out,  
the device immediately terminates the time-out period and  
suspends the erase operation.  
After the erase operation has been suspected, the system  
can read array data from any sector not selected for erasure.  
(The device “erase suspends” all sectors selected for erasure.)  
Normal read and write timings and command definitions apply.  
Reading at any address within erase-suspended sectors  
produces status data on DQ7-DQ0. The system can use DQ7,  
or DQ6 and DQ2 together, to determine if a sector is actively  
erasing or is erase-suspended. See “Write Operation Status”  
for information on these status bits.  
Sector Erase Command Sequence  
Sector erase is a six bus cycle operation. The sector erase  
command sequence is initiated by writing two unlock cycles,  
followed by a set-up command. Two additional unlock write  
cycles are then followed by the addresss of the sector to be  
erased, and the sector erase command. The Command  
Definitions table shows the address and data requirements for  
the sector erase command sequence.  
The device does not require the system to preprogram the  
memory prior to erase. The Embedded Erase algorithm  
automatically programs and verifies the sector for an all zero  
data pattern prior to electrical erase. The system is not required  
to provide any controls or timings during these operations.  
After the command sequence is written, a sector erase  
time-out of 50µs begins. During the time-out period, additional  
sector addresses and sector erase commands may be written.  
Loading the sector erase buffer may be done in any sequence,  
and the number of sectors may be from one sector to all sectors.  
The time between these additional cycles must be less than  
50µs, otherwise the last address and command might not be  
accepted, and erasure may begin. It is recommended that  
processor interrupts be disabled during this time to ensure all  
commands are accepted. The interrupts can be re-enabled after  
the last Sector Erase command is written. If the time between  
additional sector erase commands can be assumed to be less  
than 50µs, the system need not monitor DQ3. Any command  
other than Sector Erase or Erase Suspend during the time-out  
period resets the device to reading array data. The system  
must rewrite the command sequence and any additional sector  
addresses and commands.  
FIGURE 2: ERASE OPERATION  
The system can monitor DQ3 to determine if the sector  
erase timer has timed out. (See the “DQ3: Sector Erase Timer”  
section.) The time-out begins from the rising edge of the final  
WE\ pulse in the command sequence.  
Once the sector erase operation has begun, only the Erase  
Suspend command is valid. All other commands are ignored.  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are no longer  
latched. The system can determine the status of the erase  
operation by using DQ7, DQ6, or DQ2. Refer to “Write  
Operation Status” for information on these status bits.  
Figure 2 illustrates the algorithm for the erase operation.  
Refer to the Erase/Program Operations tables in the “AC  
Characteristics” section for parameters, and to the Sector Erase  
Operations Timing diagram for timing waveforms.  
Erase Suspend/Erase Resume Commands  
The Erase Suspect command allows the system to  
interrupt a sector erase operation and then read data from, or  
program data to, any sector not selected for erasure. This  
command is valid only during the sector erase operation,  
NOTE:  
1) See the appropriate Command Definitions table for program  
command sequence.  
2) See “DQ3: Sector Erase Timer” for more information.  
AS29F040  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
Rev. 2.2 09/07  
8
1...567891011...27

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