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AS1500-Z

更新时间: 2024-10-28 04:06:43
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艾迈斯 - AMSCO 数字电位计
页数 文件大小 规格书
8页 365K
描述
Digital Potentiometer

AS1500-Z 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:SOP, SOP8,.25Reach Compliance Code:unknown
风险等级:5.83转换器类型:DIGITAL POTENTIOMETER
JESD-30 代码:R-PDSO-G8端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3/5 V
认证状态:Not Qualified子类别:Digital Potentiometers
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

AS1500-Z 数据手册

 浏览型号AS1500-Z的Datasheet PDF文件第2页浏览型号AS1500-Z的Datasheet PDF文件第3页浏览型号AS1500-Z的Datasheet PDF文件第4页浏览型号AS1500-Z的Datasheet PDF文件第6页浏览型号AS1500-Z的Datasheet PDF文件第7页浏览型号AS1500-Z的Datasheet PDF文件第8页 
Data Sheet AS1500/1/2/3  
AS150x – SPECIFICATIONS  
1
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0  
DAC Register  
SD  
CK  
(VDD = 3V±10% or 5V±10%, VA = VDD, VB = 0V,  
0
1
–40°CTA+125°C unless otherwise noted.)  
0
1
0
ELECTRICAL CHARACTERISTICS–ALL  
VERSIONS  
CS  
VD  
0V  
VOUT  
Sym-  
bol  
Typ  
Parameter  
Conditions Min  
Max Unit  
21  
Figure 2: Timing Diagram  
22, 23  
SWITCHING CHARACTERISTICS  
Input Clock  
Clock Level  
1
tCH, tCL  
50  
ns  
SDI  
Pulsewidth  
High or Low  
A
X
or  
A
X
or  
tD  
0
Data Setup Time  
Data Hold Time  
CSN Setup Time  
CSN High  
tDS  
tDH  
5
5
ns  
ns  
ns  
tD  
tC  
tCSS  
10  
tCS  
1
CK  
0
tCSW  
tCSH  
tCS1  
10  
ns  
ns  
ns  
Pulsewidth  
tCL  
CK Fall to CSN Rise  
Hold Time  
tCS  
1
0
tCS  
0
CSN  
tCS  
tS  
CSN Rise to Clock  
10  
Rise Setup  
VDD  
VOUT  
0V  
±1%  
Table 5: Switching Characteristics  
±1% Error  
Figure 3: Detailed Timing Diagram  
Detailed Description  
Rheostat Operation  
The digital potentiometer family AS150x offers nominal  
Serial-Programming  
Programming of the AS150x is done via the 3 wire serial  
interface. The three input signals are serial data input  
(SDI), clock(CK) and chip select (CS). A programming  
sequence consists of 10-bit, where the last eight bit  
contain the code word for the resistor value. The first two  
bits A1 and A0 have to be low(see Table ). The data is  
shifted into the internal 10 Bit register with the rising edge  
of the CK signal. With the rising edge of the CSN signal  
the data becomes valid and the resistance is updated (see  
figure 2). A detailed block diagram is shown in figure 3.  
resistor values of 10k, 20 k, 50kand 100k. The  
resistor has 256 contact points where the wiper can access  
the resistor. The 8-bit code word determines the position  
of the wiper and is decoded through an internal logic. The  
lowest code 00h is related to the terminal B. The  
resistance is then only determined by the wiper resistance  
(100). The resistance for the next code 01h is the  
nominal resistor RAB (10k, 20 k, 50kor 100k)  
divided through 256 plus the wiper resistor. In case of  
AS1501 (10k) the total resistance is 39+100=139.  
Accordingly the resistor for code 02h is 78+100=178.  
The last code 255h does not connect to terminal A directly  
(see Figure 5). So the maximum value is 10000- 39Ω  
+100= 10061. The general formula for the calculation  
of the resistance RWB is:  
A1 A0 D7  
MSB  
D6  
D5  
D4  
Data  
D3  
D2  
D1  
D0  
LSB  
0
0
Table 6: Serial data format (16 bits)  
RWB (Dx)= (Dx)/256RAB + RW  
21  
Typicals represent average readings at 25°C and VDD=5V.  
22  
Guaranteed by design and not subject to production test.  
Resistor-terminal capacitance tests are measured with 2.5V  
bias on the measured terminal. The remaining resistor  
terminals are left open circuit.  
where RAB is the nominal resistance between terminal A  
and B, RW is the wiper resistance and DX is the 8-Bit Code  
word. In Table 7 the resistor values between the wiper and  
terminal B for AS1501 are given for specific codes DX. In  
the zero-scale condition the wiper resistance of 100Ω  
remains present.  
23  
See timing diagram for location of measured values. All input  
control voltages are specified with tR = tF = 1ns (10% to 90% of  
VDD) and timed from  
a voltage level of 1.6V. Switching  
characteristics are measured using VDD=3V or 5V. To avoid  
false clocking, a minimum input logic slew rate of 1V/µs should  
be maintained.  
Revision 1.0, Oct 2004  
Page 5 of 8  

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