Datasheet > AS1155

AS1155

更新时间： 2024-11-07 06:37:39

品牌	Logo	应用领域
艾迈斯 - AMSCO		/
页数	文件大小	规格书
15页	291K
描述
Single/Dual LVDS Receivers

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AS1155 数据手册

Data Sheet

AS1153/55/57/58

Single/Dual LVDS Receivers

1 General Description

2 Key Features

The AS1153/55/57/58 are Single/Dual flow-through

LVDS (low-voltage differential signaling) receivers which

accept LVDS differential inputs and convert them to

LVCMOS outputs. The receivers are perfect for low-

power low-noise applications requiring high signaling

rates and reduced EMI emissions.

ꢀ

Flow-Through Pinout

Guaranteed 260Mbps Data Rate

300ps Pulse Skew (Max)

Conform to ANSI TIA/EIA-644 LVDS Standards

Single +3.3V Supply

The devices are guaranteed to receive data at speeds

up to 260Mbps (130MHz) over controlled impedance

media of approximately 100Ω. Supported transmission

media are PCB traces, backplanes, and cables.

Operating Temperature Range: -40 to +85ºC

Failsafe Circuit

The AS1155/58 are single LVDS receivers, and the

AS1153/57 are dual LVDS receivers.

The AS1157/58 features integrated parallel termination

resistors (nominally 107Ω), which eliminate the require-

ment for discrete termination resistors, and reduce stub

lengths. The AS1153/55 uses high impedance inputs

and requires an external termination resistor when used

in a point-to-point connection.

Integrated Termination (AS1157/58)

8-pin SOIC Package

3 Applications

The integrated Failsafe feature sets the output high if the

inputs are open, undriven and terminated, or undriven

and shorted.

Digital Copiers, Laser Printers, Cellular Phone Base Sta-

tions, Add/Drop Muxes, Digital Cross-Connects,

DSLAMs, Network Switches/Routers, Backplane Inter-

connect, Clock Distribution Computers, Intelligent Instru-

ments, Controllers, Critical Microprocessors and

Microcontrollers, Power Monitoring, and Portable/Bat-

tery-Powered Equipment.

All inputs conform to the ANSI TIA/EIA- 644 LVDS stan-

dards. Flow-through pinout simplifies PC board layout

and reduces crosstalk by separating the LVDS inputs

and LVCMOS outputs.

The devices are available in a 8-pin SOIC package.

Figure 1. Block Diagrams

AS1155/58

AS1153/57

IN1-

IN1+

IN2+

IN2-

VCC

IN1+

OUT1

OUT2

GND

N/C

GND

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