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APXA6R3ARA681MJC0G PDF预览

APXA6R3ARA681MJC0G

更新时间： 2024-02-10 06:43:47
品牌 Logo 应用领域
美国国家半导体 - NSC 电容器
页数 文件大小 规格书
10页 1211K
描述
Evaluation Board provides the design engineer with a fully functional

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APXA6R3ARA681MJC0G 技术参数

生命周期：Active包装说明：, 4141
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：5.63电容：680 µF
电容器类型：ALUMINUM ELECTROLYTIC CAPACITOR介电材料：ALUMINUM (SOLID POLYMER)
ESR：10 m Ω高度：12.2 mm
JESD-609代码：e3长度：11 mm
安装特点：SURFACE MOUNT负容差：20%
端子数量：2最高工作温度：105 °C
最低工作温度：-55 °C封装形状：CYLINDRICAL PACKAGE
封装形式：SMT包装方法：TAPE
极性：POLARIZED正容差：20%
额定（直流）电压（URdc）：6.3 V纹波电流：5500 mA
系列：APXA(6.3V)尺寸代码：4141
表面贴装：YES端子面层：TIN
端子形状：FLAT宽度：10.3 mm
Base Number Matches：1

APXA6R3ARA681MJC0G 数据手册

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National Semiconductor  
Application Note 2066  
Eric Lee  
LM25119 Evaluation Board  
September 28, 2010  
ed to the J6 (OUT2+) and J5 (OUT2-/GND). Be sure to  
choose the correct connector and wire size when attaching  
the source power supply and the load.  
Introduction  
The LM25119EVAL evaluation board provides the design en-  
gineer with a fully functional dual output buck converter, em-  
ploying the LM25119 Dual Emulated Current Mode Syn-  
chronous Buck Controller. The evaluation board is designed  
to provide both 3.3V and 1.8V outputs over an input range of  
6.0V to 36V. Also the evaluation board can be easily config-  
ured for a single 3.3V, 16A regulator.  
SOURCE POWER  
The power supply and cabling must present low impedance  
to the evaluation board. Insufficient cabling or a high  
impedance power supply will droop during power supply ap-  
plication with the evaluation board inrush current. If large  
enough, this droop will cause a chattering condition during  
power up. During power down, insufficient cabling or a high  
impedance power supply will overshoot. This overshoot will  
cause a non-monotonic decay on the output.  
Performance of the Evaluation  
Board  
•
•
•
•
•
•
•
•
Input Voltage Range: 6.0V to 36V  
Output Voltage: 3.3V (CH1), 1.8V (CH2)  
Output Current: 8A (CH1), 8A (CH2)  
Nominal Switching Frequency: 230 KHz  
Synchronous Buck Operation: Yes  
Diode Emulation Mode: Yes  
An additional external bulk input capacitor may be required  
unless the output voltage droop/overshoot of the source pow-  
er is less than 0.5V. In this board design, UVLO setting is  
conservative while UVLO hysteresis setting is aggressive.  
Minimum input voltage can goes down with an aggressive  
design. Minimum operating input voltage depends on the out-  
put voltage droop/overshoot of the source power supply and  
the forced off-time of the LM25119. Refer to the LM25119  
datasheet for complete design information.  
Hiccup Mode Overload Protection: Yes  
External VCC Sourcing: No  
LOADING  
Powering and Loading  
Consideration  
When applying power to the LM25119 evaluation board, cer-  
tain precautions need to be followed. A misconnection can  
damage the assembly.  
When using an electronic load, it is strongly recommended to  
power up the evaluation board at light load and then slowly  
increase the load. If it is desired to power up the evaluation  
board at maximum load, resistor banks must be used. In gen-  
eral, electronic loads are best suited for monitoring steady  
state waveforms.  
PROPER BOARD CONNECTION  
AIR FLOW  
The input connections are made to the J1 (VIN) and J2 (RTN/  
GND) connectors. The CH1 load is connected to the J3  
(OUT1+) and J4 (OUT1-/GND) and the CH2 load is connect-  
Prolonged operation with high input voltage at full power will  
cause the MOSFETs to overheat. A fan with a minimum of  
200LFM should be always provided.  
30126101  
FIGURE 1. Typical Evaluation Setup  
© 2010 National Semiconductor Corporation  
301261  
www.national.com  
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