Datasheet > APTS020A0X43-SRZ

APTS020A0X43-SRZ

更新时间： 2024-02-07 00:44:09

品牌	Logo	应用领域
LINEAGEPOWER		/
页数	文件大小	规格书
26页	734K
描述
4.5 - 14Vdc input; 0.69Vdc to 5.5Vdc output; 20A output current

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APTS020A0X43-SRZ 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.75	模拟集成电路 - 其他类型：	DC-DC REGULATED POWER SUPPLY MODULE
湿度敏感等级：	2	峰值回流温度（摄氏度）：	260
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

APTS020A0X43-SRZ 数据手册

Data Sheet

12V TLynx^TMNon-isolated DC-DC Power Modules:

July 24, 2009

4.5 – 14Vdc input; 0.69Vdc to 5.5Vdc output; 20A output current

Feature Specifications

Unless otherwise indicated, specifications apply over all operating input voltage, resistive load, and temperature

conditions. See Feature Descriptions for additional information.

Parameter

Device

Symbol

Min

Typ

Max

Units

On/Off Signal Interface

(V_IN=V_{IN, min}to V_{IN, max}; open collector or equivalent,

Signal referenced to GND)

Device is with suffix “4” – Positive Logic (See Ordering

Information)

Logic High ( Module ON)

Input High Current

All

IIH

µA

⎯

Input High Voltage

VIH

V_IN– 1

V_IN,max

Logic Low (Module OFF)

Input Low Current

All

IIL

⎯

Input Low Voltage

VIL

3.5

Device Code with no suffix – Negative Logic (See Ordering

Information)

(On/OFF pin is open collector/drain logic input with

external pull-up resistor; signal referenced to GND)

Logic High (Module OFF)

Input High Current

All

IIH

―

Input High Voltage

VIH

2.0

V_{IN, max}

Vdc

Logic Low (Module ON)

Input low Current

All

IIL

―

μA

Input Low Voltage

VIL

Vdc

Turn-On Delay and Rise Times

(V_IN=V_{IN, nom}, I_O=I_{O, max ,}V_Oto within ±1% of steady state)

Case 1: On/Off input is enabled and then input power is

applied (delay from instant at which V_IN= V_{IN, min}until Vo =

10% of Vo, set)

All

Tdelay

Trise

―

msec

Case 2: Input power is applied for at least one second and

then the On/Off input is enabled (delay from instant at

which Von/Off is enabled until Vo = 10% of Vo, set)

Output voltage Rise time (time for Vo to rise from

10% of Vo, set to 90% of Vo, set)

―

msec

Output voltage overshoot (T_A= 25^oC

3.0

% V_{O, set}

V_IN= V_{IN, min}to V_{IN, max},I_O= I_{O, min}to I_{O, max}

)

With or without maximum external capacitance

Over Temperature Protection

All

T_ref

135

°C

(See Thermal Considerations section)

Sequencing Delay time

Delay from V_{IN, min}to application of voltage on SEQ pin

All

TsEQ-delay

VSEQ –Vo

msec

Tracking Accuracy

(Power-Up: 2V/ms)

150

100

(Power-Down: 2V/ms)

(V_{IN, min}to V_{IN, max}; I_{O, min}to I_{O, max}VSEQ < Vo)

Input Undervoltage Lockout

Turn-on Threshold

All

4.45

4.2

Vdc

Turn-off Threshold

Hysteresis

0.25

LINEAGE POWER

1 2 3 456 7 8...26

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