Datasheet > APL0050

APL0050

更新时间： 2024-09-25 08:32:35

品牌	Logo	应用领域
ASB		/
页数	文件大小	规格书
1页	139K
描述
PLL Module

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中文翻译

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APL0050 数据手册

Plerow APL0050

PLL Module

Features

Description

The plerow^TMPLL synthesizer module was

designed for use in wireless and wireline

systems in a wide range of frequency from

50 MHz to 6 GHz. ASB’s PLL provides

exceptionally low spurious and phase noise

performance with fast locking time and low

current consumption. All products are

available in a surface-mount type package.

· +5 dBm Output Level at 50 MHz

· Channel Step Size : 100 kHz

· 2^ndHarmonic : < -20 dBc

· Spurious Level : < -70 dBc

· Lock Time : < 10 ms

· 17 mA Current Consumption

Specifications

Max.

Parameter

Frequency Range

Output Power

Unit

MHz

dBm

Min.

Typical

More Information

Website: www.asb.co.kr

E-mail: sales@asb.co.kr

Supply Voltage

4.7

5.0

5.3

Current Consumption

Channel Step Size

2^ndHarmonics

Tel: (82) 42-528-7220

Fax: (82) 42-528-7222

ASB, Inc., 4^thFl. Venture Town

Bldg, KT HRDC, 367-17

Goijeong-Dong, Seo-Gu,

Daejeon, 302-716, Korea

kHz

dBc

100

-23

-78

-20

-70

Spurious Level

Lock Time

Reference Frequency

Reference Input Level

Phase Noise (C / N)

@ 10 kHz

MHz

dBm

-5

dBc/Hz

Ω

-112

-124

-110

-107

-118

@ 100 kHz

-121

Output Impedance

Operating Temp. Range

Package Type & Size

-40

°C

SMT, 19.0W×19.0L×5.8H

1) Measurement conditions are as follows: T = 25°C, V_CC= 5 V, Freq. = 50 MHz, 50 ohm system.

Outline Drawing

Top View

Bottom View

Dimension (mm)

Pin Configuration

CLOCK

19.0

5.8

1.5

0.5

1.75

1.35

15.0

0.9

DATA

ENABLE

OSC IN

VCC (VCO)

RF OUT

VCP (PLL)

LOCK DETECT

Ground

Others

Tolerance: ± 0.2

Side View

1/1

www.asb.co.kr

March 2004

中文翻译

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