Datasheet > AN217

AN217

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
18页	325K
描述
C8051F35X DELTA-SIGMA ADC USER’S GUIDE

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数据手册

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AN217 数据手册

AN217

SFR Definition 2.3. ADC0DECH: ADC0 Decimation Ratio Register High Byte

R/W

DECI10

Bit2

R/W

DECI9

Bit1

R/W

DECI8

Bit0

Reset Value

00000111

Bit7

Bit6

Bit5

Bit4

Bit3

SFR Address:

0x9B

Bits 7–3: Unused: Read = 00000b, Write = don’t care.

Bits 2–0: DECI[10:8]: ADC0 Decimation Ratio Register, Bits 10–8.

This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio deter-

mines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the ADC0DECL

This SFR can only be modified when ADC0 is in IDLE mode.

SFR Definition 2.4. ADC0DECL: ADC0 Decimation Ratio Register Low Byte

R/W

DECI7

Bit7

R/W

DECI6

Bit6

R/W

DECI5

Bit5

R/W

DECI4

Bit4

R/W

DECI3

Bit3

R/W

DECI2

Bit2

R/W

DECI1

Bit1

R/W

DECI0

Bit0

Reset Value

11111111

SFR Address:

0x9A

Bits 7–0: DECI[7:0]: ADC0 Decimation Ratio Register, Bits 7–0.

This register contains the low byte of the 11-bit ADC Decimation Ratio. The decimation ratio deter-

mines the number of modulator input samples used to generate a single output word from the ADC.

The ADC0 decimation ratio is defined as:

Decimation Ratio = DECI[10:0] + 1

The corresponding sampling period and output word rate of ADC0 is:

ADC0 Conversion Period = [(DECI[10:0] + 1) x 128] / MDCLK

ADC0 Output Word Rate = MDCLK / [128 x (DECI[10:0] + 1)]

The minimum decimation ratio setting is 20. Any register setting below 19 will automatically be

interpreted as 19.

Important: When using the fast filter, the decimation ratio must be divisible by 8 (DECI[2:0] =

111b).

This SFR can only be modified when ADC0 is in IDLE mode.

Rev. 0.2

1...5 6 789 10 11...18

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