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AN217

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
18页	325K
描述
C8051F35X DELTA-SIGMA ADC USER’S GUIDE

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AN217 数据手册

AN217

2.2.6. The Digital Filter

[(SIN x)/x]³

-100

-200

FREQUENCY (Hz)

Figure 4. Digital Filter Frequency Response (SINC3)

The filter’s function is to convert the 1-bit digital output of the modulator to a large digital output word (16- or 24-

bits). The series of 1s and 0s input to the filter have a spectral shape that allows the digital filter to remove the

maximum amount of noise. The filter decimates the data from the modulator to output words at a lower rate (for the

desired bandwidth of interest). The filter’s job is to remove noise from the measurement, and will do so optimally at

a high decimation ratio. There is a trade-off between noise performance and the decimation ratio (see Table 1 on

page 14). Therefore, the designermust consider the increase in noise if a higher output word rate is desired. To

obtain the best performance, the filter’s decimation ratio should be configured to the highest possible value, while

still allowing the minimum required output word rate.

The decimation ratio is set in the ADC0 Decimation Ratio High and Low registers (ADC0DECH and ADC0DECL).

These two registers are used to form an 11-bit decimation ratio value and corresponding output word rate:

DECIMATION RATIO = DECI[10:1]

Equation 2. Decimation Ratio Register Value (DECI)

Output Rate = MDCLK ⁄ [128 × (DECI + 1)]

Equation 3. ADC0 Output Word Rate

Rev. 0.2

1...4 5 678 9 10...18

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