The Analog Mixed Signal Company
Amplifier
Name
ID:
010
AMP-05
Description
This op-amp is designed for on chip signal processing, especially as a low-noise input amplifier. It uses pole splitting for
compensation. Stable operation at unity gain frequency is not feasible due to the three stage amplifier architecture. The
results are simulated with extracted parasitics. To adapt this op-amp to other demands, scale the output stage and the
Miller-caps or change the bias currents.
Conditions
Temperature
Reference Current (Iref)
VDD
27°C
10 µA
2.5 V
VSS
-2.5 V
Load
10 kOhms || 10 pF
Simulated Data
Parameter
Symbol
Unit
Min
Typ
Max
Condition
Supply Voltage
VDD
V
5
Reference Current
Supply Current
Iref
IDD
VIO
µA
µA
10
525
Unity Gain
Input Offset Voltage
mV
Unity Gain, No Parasitics, delta
L=0.1µm
0.91
TK VIO
TK(VIO)
µV/K
Unity Gain, No Parasitics, delta
L=0.1µm
9.84
122.1
Voltage Gain
v
fT
Îm
dB
MHz
deg
Transit Frequency
Phasemargin
4.2
-65
No stable operation at unity gain
possible.
0.01% Settling Time
ns
No stable operation at unity gain
possible.
Slew Rate
S
V/µs
No stable operation at unity gain
possible.
< 5 ppm
Maximum Large Signal
Frequency
Output Swing
kHz
V
VOUT
VCM
-1.13
-2
1.39
5
Static Nonlinearity
VDD = +5 V, Unity Gain
ppm
V
Commonmode Range
CMRR > 70 dB @ 10 Hz
1
CMRR > 223.2 dB @ 10 Hz
fCM= 10 kHz, VCM = 0V
fPS= 1 Hz
Common Mode Rejection Ratio CMRR
Power Supply Rejection Ratio PSRR
dB
dB
204.8
184.2