AMIS-710205-A4/AMIS-710206-A4: 200dpi CIS Modules
Data Sheet
11.0 Switching Characteristics (25°C)
The switching characteristics at 25°C for the I/O clocks are shown in Figure 4. Each switch timing characteristic for each waveform is
represented by its symbolic acronym. Each corresponding switching time is defined in Table 9.
Figure 4: Module Timing Diagram
Note: Only one video output is shown because all four videos have identical electrical characteristics. The only physical difference between the outputs is in the Section 4
output, VOUT4. Section 4 has only six sensor chips; hence, its active scan is shorter by 64 pixels (see Figure 4).
Table 9: Timing Symbol’s Definitions and Timing Values
Item
Clock cycle time
Clock pulse width
Clock duty cycle
Prohibit crossing time of Start
Pulse(1)
Symbol
Min.
0.20
50
25
0
Typ.
Max.
4.0
Units
µs
ns
%
ns
to
tw
75
tprh
Data setup time
Data hold time
Signal delay time
Signal settling time
Note:
tds
tdh
tdl
20
0
20
100
ns
ns
ns
ns
tsh
(1) "Prohibit crossing of start pulse" is used to indicate that the start pulse should not be active high between any two consecutive clock pulses; specifically, between
two consecutive low going clock pulses (see the Figure 4). All falling clock edges under an active high start pulse load the internal shift register, therefore the start
pulse must be active over only one falling clock edge. A high start pulse over all rising clock edges is ignored by the shift register. One simple way to ensure that
the start pulse will not be actively high during two consecutive falling clock edges is to generate the start pulse on a rising clock edge and terminate it on the
following rising clock edge.
AMI Semiconductor – Aug. 06, M-20608-001
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