Datasheet > AMIS-30532

AMIS-30532

更新时间： 2022-12-17 01:39:26

品牌	Logo	应用领域
安森美 - ONSEMI		驱动器电机
页数	文件大小	规格书
29页	564K
描述
Micro-Stepping Motor Driver

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数据手册

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AMIS-30532 数据手册

AMIS--30532

Registers are updated with

the internal status at the

rising edge of CS

The NEW DATA is written into the

correspondinginternal register at

the rising edge of CS

COMMAND

DATA

COMMAND

READ DATA

from ADDR2

WRITE DATA

to ADDR2

NEW DATA

for ADDR2

COMMAND

or DUMMY

DATA from previous

command or NOT VALID

after POR or RESET

DATA

NEW DATA

from ADDR2

OLD DATA

or NOT VALID

OLD DATA

fromADDR2

OLD DATA

from ADDR2

Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed

by a READ Back Operation to Confirm a Correct WRITE Operation

NOTE: The internal data--out shift buffer of AMIS--30532 is updated with the content of the selected SPI register only at the last (every

eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be

written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.

Table 13. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to “0” after power--on or

hard reset)

Structure

Bit 7

R/W

Bit 6

R/W

Bit 5

R/W

Bit 4

R/W

Bit 3

R/W

Bit 2

Bit 1

R/W

Bit 0

R/W

Content

Access

Reset

Data

R/W

Address

WR (00h)

CR0 (01h)

CR1 (02h)

CR2 (03h)

CR2 (08h)

WDEN

WDT[3:0]

Data

SM[2:0]

NXTP

SLP

CUR[4:0]

PWMJ

Data

DIRCTRL

MOTEN

PWMF

EMC[1:0]

Data

SLAG

SLAT

Data

M[1:0]

StrB[1:0]

StrC

StrE[1:0]

Where:

R/W

Reset:

Read and Write access

Status after power--On or hard reset

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