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AM79865/AM79866A?

更新时间： 2024-10-28 23:29:59
品牌 Logo 应用领域
其他 - ETC 光电二极管
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17页 112K
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Am79865/Am79866A? 110KB (PDF) Physical Data Transmitter/Physical Data Receiver ?

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AM79865/AM79866A? 数据手册

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FINAL  
Am79865/Am79866A  
Physical Data Transmitter/Physical Data Receiver  
DISTINCTIVE CHARACTERISTICS  
■ Fully compliant with ANSI X3T9.5 FDDI,  
■ The on-chip Phase-Locked-Loop (PLL) only  
TP-FDDI, and 100BASE-TX/FX PHY standards  
requires an external frequency reference  
■ 125 MBaud (100 Mbps) serial link data rate  
■ Interfaces to fiber or copper media  
■ Provides data and clock recovery functions for  
FDDI and Fast Ethernet applications  
■ Parallel input to the PDT is a 5-bit encoded NRZ  
■ Dedicated pins provide electrical loopback  
symbol clocked by LSCLK  
data path  
■ Parallel output from the PDR is a 5-bit  
■ 20-pin Plastic Leaded Chip Carrier (PLCC)  
■ Single +5 V power supply operation  
unframed NRZ symbol clocked by RSCLK  
GENERAL DESCRIPTION  
The Physical Data Transmitter (Am79865) and the  
Physical Data Receiver (Am79866) devices provide  
clock recovery/generation functions meeting the re-  
quirements of FDDI, TP-FDDI, and 100BASE-TX PHY  
standards.  
includes, among others, the 4B5B encoding and  
decoding.  
The PDT converts encoded symbols into a serial NRZI  
data stream.The on-chip PLL generates a bit rate clock  
from the LSCLK reference.  
The PDT and PDR devices are part of the SUPERNET  
2 FDDI Physical Layer Protocol chip set which also in-  
cludes the Physical Layer Controller with Scrambler  
(PLC-S).The PLC-S (Am79C864A), PDT and PDR de-  
vices are collectively known as the AmPHY.The PLC-S  
performs the FDDI physical layer functions which  
The PDR uses a built-in clock recovery PLL to extract  
clock information from the received data stream. The  
recovered clock is used for serial-to-parallel data  
conversion.  
Publication# 15451 Rev: D Amendment/0  
Issue Date: June 1996  
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