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AM42DL3224GB71IT PDF预览

AM42DL3224GB71IT

更新时间: 2024-11-13 04:32:27
品牌 Logo 应用领域
超微 - AMD 闪存内存集成电路静态存储器
页数 文件大小 规格书
64页 1060K
描述
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM

AM42DL3224GB71IT 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:BGA包装说明:LFBGA, BGA73,10X12,32
针数:73Reach Compliance Code:compliant
HTS代码:8542.32.00.71风险等级:5.23
Is Samacsys:N最长访问时间:70 ns
其他特性:PSEUDO SRAM IS ORGANISED AS 256K X 16; FLASH CAN ALSO BE ORGANISED AS 4M X 8JESD-30 代码:R-PBGA-B73
JESD-609代码:e0长度:11.6 mm
内存密度:33554432 bit内存集成电路类型:MEMORY CIRCUIT
内存宽度:16混合内存类型:FLASH+SRAM
功能数量:1端子数量:73
字数:2097152 words字数代码:2000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2MX16
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA73,10X12,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH电源:3 V
认证状态:Not Qualified座面最大高度:1.4 mm
子类别:Other Memory ICs最大压摆率:0.045 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:8 mmBase Number Matches:1

AM42DL3224GB71IT 数据手册

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PRELIMINARY  
Am42DL32x4G  
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM  
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash  
Memory and 4 Mbit (256 K x 16-Bit) Static RAM  
DISTINCTIVE CHARACTERISTICS  
SOFTWARE FEATURES  
MCP Features  
Power supply voltage of 2.7 to 3.3 volt  
Data Management Software (DMS)  
AMD-supplied software manages data programming and  
erasing, enabling EEPROM emulation  
Eases sector erase limitations  
High performance  
Flash Access time as fast as 70 ns  
SRAM access time as fast as 55 ns  
Supports Common Flash Memory Interface (CFI)  
Erase Suspend/Erase Resume  
Package  
73-Ball FBGA  
Suspends erase operations to allow programming in same  
bank  
Operating Temperature  
–40°C to +85°C  
Data# Polling and Toggle Bits  
Provides a software method of detecting the status of  
program or erase cycles  
Flash Memory Features  
Unlock Bypass Program command  
ARCHITECTURAL ADVANTAGES  
Reduces overall programming time when issuing multiple  
program command sequences  
Simultaneous Read/Write operations  
Data can be continuously read from one bank while  
executing erase/program functions in other bank  
Zero latency between read and write operations  
HARDWARE FEATURES  
Any combination of sectors can be erased  
Secured Silicon (SecSi) Sector: Extra 256 Byte sector  
Ready/Busy# output (RY/BY#)  
Factory locked and identifiable: 16 bytes available for  
secure, random factory Electronic Serial Number; verifiable  
as factory locked through autoselect function.  
Customer lockable: Sector is one-time programmable. Once  
locked, data cannot be changed  
Hardware method for detecting program or erase cycle  
completion  
Hardware reset pin (RESET#)  
Hardware method of resetting the internal state machine to  
reading array data  
Zero Power Operation  
Sophisticated power management circuits reduce power  
consumed during inactive periods to nearly zero  
WP#/ACC input pin  
Write protect (WP#) function allows protection of two outermost  
boot sectors, regardless of sector protect status  
Top or bottom boot block  
Acceleration (ACC) function accelerates program timing  
Manufactured on 0.17 µm process technology  
Compatible with JEDEC standards  
Sector protection  
Hardware method of locking a sector, either in-system or  
using programming equipment, to prevent any program or  
erase operation within that sector  
Pinout and software compatible with single-power-supply  
flash standard  
Temporary Sector Unprotect allows changing data in  
protected sectors in-system  
PERFORMANCE CHARACTERISTICS  
High performance  
Access time as fast as 70 ns  
SRAM Features  
Power dissipation  
Program time: 4 µs/word typical utilizing Accelerate function  
Ultra low power consumption (typical values)  
Operating: 22 mA maximum for 70 ns, 30 mA maximum for  
2 mA active read current at 1 MHz  
55 ns  
10 mA active read current at 5 MHz  
200 nA in standby or automatic sleep mode  
Standby: 10 µA maximum  
CE1s# and CE2s Chip Select  
Minimum 1 million write cycles guaranteed per sector  
20 Year data retention at 125°C  
Power down features using CE1s# and CE2s  
Data retention supply voltage: 1.5 to 3.3 volt  
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)  
Reliable operation for the life of the system  
This document contains information on a product under development at Advanced Micro Devices. The information  
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed  
product without notice.  
Publication# 25822 Rev: B Amendment/0  
Issue Date: May 19, 2003  
Refer to AMD’s Website (www.amd.com) for the latest information.  

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