PRELIMINARY
Am29PL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 16 Mbit Page Mode device
■ Sector Protection
— Byte (8-bit) or word (16-bit) mode selectable via
BYTE# pin
— A hardware method of locking a sector to prevent
any program or erase operations within that
sector
— Page size of 16 bytes/8 words: Fast page read
access from random locations within the page
— Sectors can be locked via programming
equipment
■ Single power supply operation
— Temporary Sector Unprotect command
sequence allows code changes in previously
locked sectors
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Minimum 1 million write cycles guarantee
per sector
■ 20-year data retention
■ 5 V-tolerant data, address, and control signals
■ High performance read access times
■ Manufactured on 0.32 µm process technology
■ Software command-set compatible with JEDEC
— Page access times as fast as 25 ns at industrial
temperature range
standard
— Backward compatible with Am29F and Am29LV
families
— Random access times as fast as 65 ns
■ Power consumption (typical values at 5 MHz)
— 30 mA read current
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
— 20 mA program/erase current
— 1 µA standby mode current
■ Unlock Bypass Program Command
— 1 µA Automatic Sleep mode current
■ Flexible sector architecture
— Reduces overall programming time when
issuing multiple program command sequences
— Sector sizes: One 16 Kbyte, two 8 Kbyte, one
224 Kbyte, and seven sectors of 256 Kbytes
each
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
— Supports full chip erase
■ Top or bottom boot block configurations
■ Package Options
available
— 44-pin SO (mask-ROM compatible pinout)
Publication# 22143 Rev: B Amendment/+6
Issue Date: September 2, 1999
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.