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AM29F400AT-90SI PDF预览

AM29F400AT-90SI

更新时间: 2024-11-04 05:26:35
品牌 Logo 应用领域
超微 - AMD 闪存
页数 文件大小 规格书
35页 140K
描述
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory

AM29F400AT-90SI 数据手册

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PRELIMINARY  
Am29F400AT/Am29F400AB  
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only,  
Sector Erase Flash Memory  
DISTINCTIVE CHARACTERISTICS  
5.0 V ± 10% for read and write operations  
Embedded Program Algorithms  
— Minimizes system level power requirements  
— Automatically programs and verifies data at  
specified address  
Compatible with JEDEC-standards  
Data Polling andToggle Bit feature for detection  
— Pinout and software compatible with  
single-power-supply flash  
of program or erase cycle completion  
Ready/Busy output (RY/BY)  
— Superior inadvertent write protection  
— Hardware method for detection of program or  
erase cycle completion  
Package options  
— 44-pin SO  
Erase Suspend/Resume  
— 48-pin TSOP  
— Supports reading data from a sector not being  
erased  
Minimum 100,000 write/erase cycles guaranteed  
High performance  
Low power consumption  
— 60 ns maximum access time  
— 20 mA typical active read current for Byte Mode  
— 28 mA typical active read current for Word Mode  
— 30 mA typical program/erase current  
Sector erase architecture  
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and  
seven 64 Kbytes  
Enhanced power management for standby  
— Any combination of sectors can be erased. Also  
supports full chip erase.  
mode  
— 1 µA typical standby current  
Sector protection  
Boot Code Sector Architecture  
— T = Top sector  
— Hardware method that disables any combination  
of sectors from write or erase operations.  
Implemented using standard PROM  
programming equipment.  
— B = Bottom sector  
Hardware RESET pin  
Embedded Erase Algorithms  
— Resets internal state machine to the read mode  
— Automatically preprograms and erases the chip  
or any sector  
GENERAL DESCRIPTION  
The Am29F400A is a 4 Mbit, 5.0Volt-only Flash memory  
organized as 512 Kbytes of 8 bits each or 256 Kwords  
of 16 bits each. The 4 Mbits of data is divided into 11  
sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte,  
and seven 64 Kbytes, for flexible erase capability. The  
8 bits of data will appear on DQ0–DQ7 or 16 bits on  
DQ0–DQ15. The Am29F400A is offered in 44-pin SO  
and 48-pin TSOP packages. This device is designed  
to be programmed in-system with the standard system  
The standard Am29F400A offers access times of  
60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high  
speed microprocessors to operate without wait states.  
To eliminate bus contention the device has sepa-  
rate chip enable (CE), write enable (WE) and output  
enable (OE) controls.  
The Am29F400A is entirely command set compatible  
with the JEDEC single-power-supply Flash standard.  
Commands are written to the command register using  
standard microprocessor write timings. Register con-  
tents serve as input to an internal state-machine  
which controls the erase and programming circuitry.  
5.0 Volt V  
supply. 12.0 Volt V is not required for  
CC  
PP  
program or erase operations.The device can also be re-  
programmed in standard EPROM programmers.  
This document contains information on a product under development at Advanced Micro Devices. The information  
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed  
product without notice.  
Publication# 20380 Rev: B Amendment/0  
Issue Date: April 1997  

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