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AM28F512-120EC

更新时间: 2024-11-08 22:24:39
品牌 Logo 应用领域
超微 - AMD 闪存
页数 文件大小 规格书
35页 460K
描述
512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory

AM28F512-120EC 数据手册

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FINAL  
Am28F512  
512 Kilobit (64 K x 8-Bit)  
CMOS 12.0 Volt, Bulk Erase Flash Memory  
DISTINCTIVE CHARACTERISTICS  
High performance  
Latch-up protected to 100 mA  
from -1 V to VCC +1 V  
— 70 ns maximum access time  
CMOS Low power consumption  
— 30 mA maximum active current  
— 100 µA maximum standby current  
— No data retention power consumption  
Flasherase Electrical Bulk Chip-Erase  
— One second typical chip-erase  
Flashrite Programming  
— 10 µs typical byte-program  
— One second typical chip program  
Compatible with JEDEC-standard byte-wide  
32-Pin EPROM pinouts  
Command register architecture for  
microprocessor/microcontroller compatible  
write interface  
— 32-pin PDIP  
— 32-pin PLCC  
— 32-pin TSOP  
On-chip address and data latches  
Advanced CMOS flash memory technology  
— Low cost single transistor memory cell  
Automatic write/erase pulse stop timer  
10,000 write/erase cycles minimum  
±
Write and erase voltage 12.0 V 5%  
GENERAL DESCRIPTION  
The Am28F512 is a 512 K bit Flash memory orga-  
nized as 64 Kbytes of 8 bits each. AMD’s Flash mem-  
ories offer the most cost-effective and reliable read/  
write non-volatile random access memory. The  
Am28F512 is packaged in 32-pin PDIP, PLCC, and  
TSOP versions. It is designed to be reprogrammed  
and erased in-system or in standard EPROM pro-  
grammers. The Am28F512 is erased when shipped  
from the factory.  
gramming mechanisms. In addition, the combination of  
advanced tunnel oxide processing and low internal  
electric fields for erase and programming operations  
produces reliable cycling. The Am28F512 uses a  
12.0V± 5% VPP high voltage input to perform the  
Flasherase and Flashrite algorithms.  
The highest degree of latch-up protection is achieved  
with AMD’s proprietary non-epi process. Latch-up pro-  
tection is provided for stresses up to 100 mA on ad-  
dress and data pins from -1 V to VCC +1 V.  
The standard Am28F512 offers access times as fast as  
70 ns, allowing operation of high-speed microproces-  
sors without wait states. To eliminate bus contention,  
the Am28F512 has separate chip enable (CE#) and  
output enable (OE#) controls.  
The Am28F512 is byte programmable using 10 ms pro-  
gramming pulses in accordance with AMD’s Flashrite  
programming algorithm. The typical room temperature  
programming time of the Am28F512 is one second.  
The entire chip is bulk erased using 10 ms erase pulses  
according to AMD’s Flasherase algorithm. Typical era-  
sure at room temperature is accomplished in less than  
one second. The windowed package and the 15-20  
minutes required for EPROM erasure using ultra-violet  
light are eliminated.  
AMD’s Flash memories augment EPROM functionality  
with in-circuit electrical erasure and programming. The  
Am28F512 uses a command register to manage this  
functionality, while maintaining a standard JEDEC  
Flash Standard 32-pin pinout. The command register  
allows for 100% TTL level control inputs and fixed  
power supply levels during erase and programming.  
Commands are written to the command register using  
standard microprocessor write timings. Register con-  
tents serve as inputs to an internal state-machine which  
controls the erase and programming circuitry. During  
AMD’s Flash technology reliably stores memory con-  
tents even after 10,000 erase and program cycles. The  
AMD cell is designed to optimize the erase and pro-  
Publication# 11561 Rev: G Amendment/+2  
Issue Date: January 1998  

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