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AM27C1024-150JI PDF预览

AM27C1024-150JI

更新时间: 2024-01-25 10:01:38
品牌 Logo 应用领域
飞索 - SPANSION OTP只读存储器
页数 文件大小 规格书
12页 177K
描述
OTP ROM, 64KX16, 150ns, CMOS, PQCC44, PLASTIC, LCC-44

AM27C1024-150JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ, LDCC44,.7SQ
针数:44Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.83最长访问时间:150 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J44
JESD-609代码:e0内存密度:1048576 bit
内存集成电路类型:OTP ROM内存宽度:16
功能数量:1端子数量:44
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
最大待机电流:0.0001 A子类别:OTP ROMs
最大压摆率:0.05 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

AM27C1024-150JI 数据手册

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FINAL  
Am27C1024  
1 Megabit (65 K x 16-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
±10% power supply tolerance standard  
100% Flashrite™ programming  
— Speed options as fast as 55 ns  
Low power consumption  
— 20 µA typical CMOS standby current  
JEDEC-approved pinout  
— 40-Pin DIP/PDIP  
Typical programming time of 8 seconds  
Latch-up protected to 100 mA from –1 V to  
VCC + 1 V  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
— 44-Pin PLCC  
Single +5 V power supply  
GENERAL DESCRIPTION  
The Am27C1024 is a 1 Megabit, ultraviolet erasable  
programmable read-only memory. It is organized as 64  
Kwords by 16 bits per word, operates from a single  
+5 V supply, has a static standby mode, and features  
fast single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 125 mW in active mode,  
and 100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 8 seconds.  
Data can be typically accessed in less than 55 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ15  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE#  
CE#  
Output  
Buffers  
Prog Logic  
PGM#  
Y
Y
Gating  
Decoder  
A0–A15  
Address  
Inputs  
1,048,576  
Bit Cell  
Matrix  
X
Decoder  
06780J-1  
Publication# 06780 Rev: J Amendment/0  
Issue Date: May 1998  

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