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AM27C010-200JC5 PDF预览

AM27C010-200JC5

更新时间: 2024-11-11 22:53:47
品牌 Logo 应用领域
超微 - AMD 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
13页 168K
描述
1 Megabit (128 K x 8-Bit) CMOS EPROM

AM27C010-200JC5 数据手册

 浏览型号AM27C010-200JC5的Datasheet PDF文件第2页浏览型号AM27C010-200JC5的Datasheet PDF文件第3页浏览型号AM27C010-200JC5的Datasheet PDF文件第4页浏览型号AM27C010-200JC5的Datasheet PDF文件第5页浏览型号AM27C010-200JC5的Datasheet PDF文件第6页浏览型号AM27C010-200JC5的Datasheet PDF文件第7页 
FINAL  
Am27C010  
1 Megabit (128 K x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
Latch-up protected to 100 mA from –1 V to  
VCC + 1 V  
— Speed options as fast as 45 ns  
Low power consumption  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
— 20 µA typical CMOS standby current  
JEDEC-approved pinout  
Single +5 V power supply  
Standard 28-pin DIP, PDIP, and 32-pin PLCC  
±10% power supply tolerance standard  
100% Flashrite™ programming  
Typical programming time of 16 seconds  
packages  
GENERAL DESCRIPTION  
The Am27C010 is a 1 Megabit, ultraviolet erasable pro-  
grammable read-only memory. It is organized as 128K  
words by 8 bits per word, operates from a single +5 V  
supply, has a static standby mode, and features fast  
single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 100 mW in active mode,  
and 100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 16 seconds.  
Data can be typically accessed in less than 45 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ7  
CC  
V
V
SS  
PP  
OE#  
CE#  
Output Enable  
Chip Enable  
and  
Output  
Buffers  
Prog Logic  
PGM#  
Y
Y
Gating  
Decoder  
A0–A16  
Address  
Inputs  
1,048,576  
Bit Cell  
Matrix  
X
Decoder  
10205G-1  
Publication# 10205 Rev: G Amendment/0  
Issue Date: May 1998  

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