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ALVD-FREQ-N-H-C PDF预览

ALVD-FREQ-N-H-C

更新时间: 2024-11-06 03:32:07
品牌 Logo 应用领域
ABRACON /
页数 文件大小 规格书
3页 1087K
描述
CMOS Output Clock Oscillator, 0.75MHz Min, 800MHz Max, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN

ALVD-FREQ-N-H-C 数据手册

 浏览型号ALVD-FREQ-N-H-C的Datasheet PDF文件第2页浏览型号ALVD-FREQ-N-H-C的Datasheet PDF文件第3页 
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR  
WITH VOLTAGE CONTROL  
ALVD  
RoHS  
7.0 x 5.0 x 1.8m m  
Pb  
Compliant  
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FEATURES:  
APPLICATIONS:  
• Based on a proprietary digital multiplier  
• Tri-State Output  
• SONET, xDSL  
• SDH, CPE  
• STB  
• Low Phase Jitter  
• 3.3V +/- 5% operation  
• Ceramic SMD, low profile package  
STANDARD SPECIFICATIONS:  
ARAMETERS  
P
ABRACON P/N:  
ALVD Series  
Frequency range:  
750 KHz to 800 MHz  
Operating temperature:  
Storage temperature:  
0°C to +70°C (see options)  
-55°C to +125°C  
Overall frequency stability:  
Supply voltage (V dd):  
±50 ppm max. (see options)  
3.3V ± 10%  
Voltage control (V C):  
Symmetry at 1/2 Vdd:  
Output Level:  
0.3VDC min, 1.65VDC typ, 3.0 VDC max.  
40/60% max.  
See options (PECL, CMOS, or LVDS)  
± 50ppm (see option)  
Pullability:  
Tristate Function:  
"1" (V IH >= 0.7* Vdd) or open: Oscillation  
"0" (V IL < 0.3* Vdd) : Hi Z  
Aging per year:  
±5 ppm max.  
3ps typical, 5ps max. (12KHz~20MHz)  
RMS Phase Jitter:  
Period Jitter (peak to peak):  
Phase Noise:  
35 ps typical  
-112 dBc/Hz @ 1kHz Offset from 155.52MHz  
-125 dBc/Hz @ 10kHz Offset from 155.52MHz  
-123 dBc/Hz @ 100KHz Offset from 155.52MHz  
-109 dBc/Hz @ 1kHz Offset from 622.08MHz  
-110 dBc/Hz @ 10kHz Offset from 622.08MHz  
-109 dBc/Hz @ 100KHz Offset from 622.08MHz  
PECL:  
Supply current (IDD):  
25mA max (for Fo<24MHz),65mA max (for 24MHz<Fo<96MHz),100mA max (96MHz<Fo<800MHz)  
Output Logic High: Vdd -1.025V min, V -0.880V max.  
dd  
Output Logic Low: Vdd -1.810V min. Vdd -1.620V max.  
Symmetry (Duty Cycle): 45% min, 50% typ, 55% max,  
Rise time: 0.6nSec typ,1.5nS max  
Fall time: 0.6nSec typ, 1.5nS max  
CMOS:  
Supply current (I  
):15  
DD  
mA max (for Fo<24MHz),30mA max (for 24MHz<Fo<96MHz), 40mA max (96MHz<Fo<800MHz)  
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]: 1.2ns typ, 1.6ns max.  
Output Clock Duty Cycle [Measured @ 50% VDD]:  
LVDS:  
45% min, 50% typical, 55% max  
Supply current (IDD):25mA max (for Fo<24MHz),45mA max (for 24MHz<Fo<96MHz),80mA max (96MHz<Fo<800MHz)  
Output Clock Duty Cycle @ 1.25V: 45% min, 50% typical, 55% max  
Output Differential Voltage (VOD): 247mV min, 355mV typical, 454mV max  
VDD Magnitude Change (VOD): -50mV min, 50mV max  
Output High Voltage : VOH = 1.4V typical, 1.6V max.  
Output Low Voltage: VOL = 0.9V min, 1.1V typical  
Offset Voltage [RL = 100 Ω]: VOS = 1.125V min, 1.2V typical, 1.375V max  
Offset Magnitude Change [RL = 100 Ω]: VOS = 0mV min, 3mV typical, 25mV max  
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] = ±1µA typical, ±10 µA max.  
Differential Clock Rise Time (tr) [RL=100 , CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS,max  
Differential Clock Fall Time (tf) [RL=100 , CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS max  
Visit www.abracon.com for Terms & Conditions of Sale Revised: 12.02.10  
30332 Esperanza, Rancho Santa Margarita, California 92688  
tel 949-546-8000 | fax 949-546-8001| www.abracon.com  
ABRACON IS  
ISO9001:2008  
CERTIFIED  
CERTIFIED  

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