Datasheet > ALD-187.5MHZ-D-H-L-T

ALD-187.5MHZ-D-H-L-T

更新时间： 2024-10-30 03:39:07

品牌	Logo	应用领域
ABRACON		/
页数	文件大小	规格书
2页	308K
描述
LVDS Output Clock Oscillator, 187.5MHz Nom, CERAMIC, SMD, 6 PIN

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ALD-187.5MHZ-D-H-L-T 数据手册

浏览型号ALD-187.5MHZ-D-H-L-T的Datasheet PDF文件第2页

CERAMIC SMD CRYSTAL CLOOCK OSCILLATTOORR

ALD SERIES

: PRELIMINARY

5.08 x 7.0 x 1.8mm

APPLICATIONS:

• SONET, xDSL

• SDH, CPE

• STB

FEATURES:

• Based on a proprietary digital multiplier

• Tri-State Output

• 2.5V to 3.3V +/- 5% operation

• Ceramic SMD, low profile package

• 156.25MHz, 187.5MHz, and 212.5MHz applications

• Low Phase Jitter

STANDARD SPECIFICATIONS:

PARAMETERS

Frequency Range

750 KHz to 800 MHz

0°C to + 70°C (see options)

- 40°C to + 85°C

50 ppm maꢀx (see options)

2x5V to 3x3 Vdc 5ꢁ

5ꢁ typ, 10ꢁ maꢀx

Operating Temperature

Storage Temperature

Overall Frequency Stability

Supply Voltage (Vdd)

Linearity

Jitter (12KHz - 20MHz)

RMS phase jitter 3pS typx < 5pS maꢀx

period jitter < 35pS peak to peak

Phase Noise

-109 dBc/Hz @ 1kHz Offset from 622x08MHz

-110 dBc/Hz @ 10kHz Offset from 622x08MHz

-109 dBc/Hz @ 100kHz Offset from 622x08MHz

“1” (V_IH> 0x7*V_DD) or open: Oscillation/ “0” (V_IH> 0x3*V_DD) No Oscillation/Hi Z

Tri-State Function

PECL

Supply Current (I_DD)

Symmetry (Duty Cycle)

Output Logic High

Output Logic Low

Clock Rise time (t_r) @ 20/80ꢁ

Clock Fall time (t_f) @ 80/20ꢁ

80mA (Fo < 155x52MHz), 100mA (Fo < 155x52MHz)

45ꢁ min, 50ꢁ typical, 55ꢁ maꢀx

V_DD-1x025V min, V_DD-0x880V maꢀx

V_DD-1x810V min, V_DD-1x620V maꢀx

1x5ns maꢀ, 0x6nSec typical

CMOS

Output Clock Rise/ Fall Time [10ꢁ~90ꢁ VDD with 10pF load] 1x6ns maꢀ, 1x2ns typical

Output Clock Duty Cycle [Measured @ 50ꢁ VDD]

45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ

LVDS

Supply Current (I_DD) [Fout = 212x50MHz]

60mA maꢀ, 55mA typicalx

Output Clock Duty Cycle @ 1x25V

45ꢁ min, 50ꢁ typical, 55ꢁ maꢀ

247mV min, 355mV typical, 454mV maꢀ

-50mV min, 50mV maꢀ

Output Differential Voltage (V_OD

)

VDD Magnitude Change (∆V_OD

)

Output High Voltage

Output Low Voltage

Offset Voltage [R_L= 100

Offset Magnitude Voltage[RL = 100

Power-off Leakage (I_OXD) [Vout=VDD or GND, VDD=0V]

Differential Clock Rise Time (t_r) [R_L=100 , CL=10pF]

Differential Clock Fall Time (t_f) [R_L=100 , CL=10pF]

V_OH= 1x6V maꢀ, 1x4V typical

V_OL= 0x9V min, 1x1V typical

Ω]

V_OS= 1x125V min, 1x2V typical, 1x375V maꢀ

∆V_OS= 0mV min, 3mV typical, 25mV maꢀ

10µA maꢀ, 1µA typical

0x2ns min, 0x5ns typical, 0x7ns maꢀ

Ω]

Ω

ABBRRAACCOONN IIS

ISO 9001 / QS 9000

CERTTIIFFIED

30332 Esperanza, Rancho Santa Margarita, California 92688

tel 949-546-8000 | fax 949-546-8001 | www.abracon.com

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与ALD-187.5MHZ-D-H-L-T相关器件

型号	品牌	获取价格	描述	数据表
ALD-187.5MHZ-D-H-P1-A-T	ABRACON	获取价格	PECL Output Clock Oscillator, 187.5MHz Nom, ROHS COMPLIANT, LOW PROFILE, CERAMIC, SMD, 6 P
ALD-187.5MHZ-D-H-P1-T	ABRACON	获取价格	PECL Output Clock Oscillator, 187.5MHz Nom, CERAMIC, SMD, 6 PIN
ALD-187.5MHZ-D-H-P-A-T	ABRACON	获取价格	PECL Output Clock Oscillator, 187.5MHz Nom, ROHS COMPLIANT, LOW PROFILE, CERAMIC, SMD, 6 P
ALD-187.5MHZ-D-H-P-T	ABRACON	获取价格	PECL Output Clock Oscillator, 187.5MHz Nom, CERAMIC, SMD, 6 PIN
ALD-187.5MHZ-D-H-V-A-T	ABRACON	获取价格	LVDS Output Clock Oscillator, 187.5MHz Nom, ROHS COMPLIANT, LOW PROFILE, CERAMIC, SMD, 6 P
ALD-187.5MHZ-D-K-C-A-T	ABRACON	获取价格	CMOS Output Clock Oscillator, 187.5MHz Nom, ROHS COMPLIANT, LOW PROFILE, CERAMIC, SMD, 6 P
ALD-187.5MHZ-D-K-C-T	ABRACON	获取价格	CMOS Output Clock Oscillator, 187.5MHz Nom, CERAMIC, SMD, 6 PIN
ALD-187.5MHZ-D-K-L-T	ABRACON	获取价格	LVDS Output Clock Oscillator, 187.5MHz Nom, CERAMIC, SMD, 6 PIN
ALD-187.5MHZ-D-K-P1-A-T	ABRACON	获取价格	PECL Output Clock Oscillator, 187.5MHz Nom, ROHS COMPLIANT, LOW PROFILE, CERAMIC, SMD, 6 P
ALD-187.5MHZ-D-K-P1-T	ABRACON	获取价格	PECL Output Clock Oscillator, 187.5MHz Nom, CERAMIC, SMD, 6 PIN

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