Datasheet > ALD-156.250MHZ-L-H-C

ALD-156.250MHZ-L-H-C

更新时间： 2024-10-29 04:07:39

品牌	Logo	应用领域
ABRACON		/
页数	文件大小	规格书
4页	1272K
描述
Oscillator

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数据手册

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ALD-156.250MHZ-L-H-C 数据手册

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PECL/LVDS/CMOS OUTPUT SMD

CRYSTAL CLOCK OSCILLATOR

RoHS

ALD SERIES

5.0 x 7.0 x 1.8mm

Compliant

FEATURES:

APPLICATIONS:

• Based on a proprietary digital multiplier

• Tri-State Output

• 2.5V to 3.3V +/- 5% operation

• Ceramic SMD, low profile package

• SONET, xDSL

• SDH, CPE

• STB

• Low Phase Noise and Jitter

• 156.25MHz, 187.5MHz, and 212.5MHz applications

STANDARD SPECIFICATIONS:

PARAMETERS

ABRACON P/N:

ALD Series

Frequency range:

Operating temperature:

Storage temperature:

Overall frequency stability:

Supply voltage (Vdd):

Jitter:

750 kHz to 800 MHz

0° C to + 70° C (see options)

- 55° C to + 125° C

± 50 ppm max. (see options)

3.3V ±10% (see options)

RMS phase jitter 3ps typ., <5ps max. (12KHz - 20MHz)

Period jitter peak to peak ,35ps typical

Low Phase Noise:

-109 dBc/Hz @ 1kHz Offset from 622.08MHz

-110 dBc/Hz @ 10kHz Offset from 622.08MHz

-109 dBc/Hz @ 100KHz Offset from 622.08MHz

-112 dBc/Hz @ 1kHz Offset from 155.52MHz

-125 dBc/Hz @ 10kHz Offset from 155.52MHz

-123 dBc/Hz @ 100KHz Offset from 155.52MHz

Tristate Function:

"1" (V ≥ 0.7*Vdd) or open: Oscillation

"0" (V < 0.3*Vdd): No Oscillation / Hi Z

Supply current (I_DD): 65mA max (for 750kHz < Fo < 96MHz), 100mA max (96MHz ≤ Fo < 800MHz)

Output Logic High: V_dd-1.025V min, V_dd-0.880V max.

Output Logic Low: V_dd-1.810V min. V_dd-1.620V max.

Symmetry (Duty Cycle): 45% min, 50% typ, 55% max,

Rise time: 0.85ns

PECL:

LVDS

Fall time: 0.85ns

Supply current (I_DD): 65mA max (for 750kHz < Fo < 96MHz), 100mA max (96MHz ≤ Fo < 800MHz)

Output Clock Duty Cycle @ 1.25V: 45% min, 50% typical, 55% max

Output Differential Voltage (V _OD): 247mV min, 355mV typical, 454mV max

VDD Magnitude Change (ΔV_OD): -50mV min, 50mV max

Output High Voltage : V_OH= 1.4V typical, 1.6V max.

Output Low Voltage: V_OL= 0.9V min, 1.1V typical

Offset Voltage [R_L= 100Ω]: V_OS= 1.125V min, 1.2V typical, 1.375V max

Offset Magnitude Change [R _L= 100Ω]: ΔV_OS= 0mV min, 3mV typical, 25mV max

Power-off Leakage (I _OXD) [Vout=VDD or GND, VDD=0V] = ±1μA typical, ±10μA max.

Differential Clock Rise Time (t _r) [R_L=100Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS,max

Differential Clock Fall Time (t _f) [R_L=100Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS max

Supply current (I_DD):15mA max (for 750kHz < Fo < 24MHz), 30mA max (for 24MHz ≤ Fo < 96MHz),

CMOS:

65mA max (96MHz ≤ Fo < 800MHz)

Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]: 5.0ns max (for 750kHz < Fo < 24MHz)

5.0ns max (for 24MHz ≤ Fo < 800MHz)

Output Clock Duty Cycle [Measured @ 50% VDD]: 45% min, 50% typical, 55% max

^{Visit www.abracon.com for Terms & Conditions of Sale}Revised: 05.20.10

30332 Esperanza, Rancho Santa Margarita, California 92688

tel 949-546-8000 | fax 949-546-8001| www.abracon.com

ABRACON IS

ISO9001:2008

CERTIFIED

12 3 4

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