Datasheet > AL1I-67204V-55

AL1I-67204V-55

更新时间： 2024-01-12 16:31:51

品牌	Logo	应用领域
TEMIC		先进先出芯片
页数	文件大小	规格书
16页	145K
描述
FIFO, 4KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28

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技术参数
数据手册

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AL1I-67204V-55 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.84
最长访问时间：	55 ns	周期时间：	70 ns
JESD-30 代码：	R-GDIP-T28	长度：	37.25 mm
内存密度：	36864 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	4096 words	字数代码：	4000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	4KX9
可输出：	NO	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.72 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	NO
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	15.24 mm
Base Number Matches：	1

AL1I-67204V-55 数据手册

MATRA MHS

L 67203/L 67204

Pin Names

NAMES

I0–8

Q0–8

DESCRIPTION

NAMES

DESCRIPTION

Inputs

XO/HF

Full Flag

Outputs

Expansion Out/Half–Full Flag

Expansion IN

Write Enable

Read Enable

Reset

FL/RT

VCC

GND

First Load/Retransmit

Power Supply

Empty Flag

Ground

Signal Description

pointers to the first location. A reset is required after

power-up before a write operation can be enabled. Both

the Read Enable (R) and Write Enable (W) inputs must be

in the high state during the period shown in figure 1 (i.e.

Data In (I0 - I8)

Data inputs for 9 - bit data

before the rising edge of RS) and should not change

RSS

Reset (RS)

until t

after the rising edge of RS. The Half-Full Flag

RSR

(HF) will be reset to high after Reset (RS).

Reset occurs whenever the Reset (RS) input is taken to a

low state. Reset returns both internal read and write

Figure 1. Reset.

Notes : 1. EF, FF and HF may change status during reset, but flags will be valid at t

RSC

2. W and R = V around the rising edge of RS.

will be set to low and remain in this state until the

difference between the write and read pointers is less than

or equal to half the total available memory in the device.

The Half-Full Flag (HF) is then reset by the rising edge

of the read operation.

Write Enable (W)

A write cycle is initiated on the falling edge of this input

if the Full Flag (FF) is not set. Data set-up and hold times

must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the

Ram array, regardless of any current read operation.

To prevent data overflow, the Full Flag (FF) will go low,

inhibiting further write operations. On completion of a

valid read operation, the Full Flag (FF) will go high after

TRFF, allowing a valid write to begin. When the FIFO

Once half the memory is filled, and during the falling

edge of the next write operation, the Half-Full Flag (HF)

Rev. C (10/11/94)

1 234 5 6 7...16

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与AL1I-67204V-55相关器件

型号	品牌	描述	获取价格	数据表
AL1I-67204V-60	TEMIC	FIFO, 4KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67204V-65	ATMEL	FIFO, 4KX9, 65ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-55	TEMIC	FIFO, 8KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-60	TEMIC	FIFO, 8KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-65	TEMIC	FIFO, 8KX9, 65ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205V-55	TEMIC	FIFO, 8KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格

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